diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/arch_mips.cpp | 6 | ||||
| -rw-r--r-- | arch/mips/il.cpp | 5 |
2 files changed, 8 insertions, 3 deletions
diff --git a/arch/mips/arch_mips.cpp b/arch/mips/arch_mips.cpp index 6150e578..51a5d411 100644 --- a/arch/mips/arch_mips.cpp +++ b/arch/mips/arch_mips.cpp @@ -332,10 +332,12 @@ protected: result.AddBranch(CallDestination, instr.operands[0].immediate, nullptr, hasBranchDelay); break; - //Jmp to register register value is unknown case MIPS_JALR: case MIPS_JALR_HB: - result.delaySlots = 1; + if (instr.operands[0].reg == REG_ZERO && instr.operands[1].reg == REG_RA) + result.AddBranch(FunctionReturn, 0, nullptr, hasBranchDelay); + else + result.AddBranch(UnresolvedBranch, 0, nullptr, hasBranchDelay); break; case MIPS_BGEZAL: diff --git a/arch/mips/il.cpp b/arch/mips/il.cpp index bfbfeeed..5700acbc 100644 --- a/arch/mips/il.cpp +++ b/arch/mips/il.cpp @@ -1430,7 +1430,10 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu { operand = 2; } - il.AddInstruction(il.Call(ReadILOperand(il, instr, operand, registerSize(instr.operands[operand]), addrSize, true))); + if (operand == 2 && op1.reg == REG_ZERO && op2.reg == REG_RA) + il.AddInstruction(il.Return(il.Register(addrSize, REG_RA))); + else + il.AddInstruction(il.Call(ReadILOperand(il, instr, operand, registerSize(instr.operands[operand]), addrSize, true))); } break; case MIPS_JR: |