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Diffstat (limited to 'arch')
-rw-r--r--arch/mips/arch_mips.cpp53
-rw-r--r--arch/powerpc/arch_ppc.cpp5
-rw-r--r--arch/powerpc/il.cpp12
3 files changed, 62 insertions, 8 deletions
diff --git a/arch/mips/arch_mips.cpp b/arch/mips/arch_mips.cpp
index 83d7a98d..85e545f6 100644
--- a/arch/mips/arch_mips.cpp
+++ b/arch/mips/arch_mips.cpp
@@ -3001,6 +3001,7 @@ public:
}
};
+
class MipsImportedFunctionRecognizer: public FunctionRecognizer
{
private:
@@ -3021,9 +3022,15 @@ private:
if (lui.operation != LLIL_SET_REG)
return false;
LowLevelILInstruction luiOperand = lui.GetSourceExpr<LLIL_SET_REG>();
+ if (luiOperand.operation == LLIL_SX)
+ luiOperand = luiOperand.GetSourceExpr<LLIL_SX>();
+ if (luiOperand.operation == LLIL_ZX)
+ luiOperand = luiOperand.GetSourceExpr<LLIL_ZX>();
+
if (!LowLevelILFunction::IsConstantType(luiOperand.operation))
return false;
- if (luiOperand.size != func->GetArchitecture()->GetAddressSize())
+ // mips64 is going to load this in two 32-bit halves, so it shouldn't be address size
+ if (luiOperand.size < 4)
return false;
uint64_t pltHi = luiOperand.GetConstant();
uint32_t pltReg = lui.GetDestRegister<LLIL_SET_REG>();
@@ -3056,7 +3063,7 @@ private:
ldAddrRightOperandValue = -ldAddrRightOperandValue;
entry = pltHi + ldAddrRightOperandValue;
}
- else if (ldAddrOperand.operation != LLIL_REG) //If theres no constant
+ else if (ldAddrOperand.operation != LLIL_REG) // If there's no constant
return false;
Ref<Symbol> sym = data->GetSymbolByAddress(entry);
@@ -3070,6 +3077,11 @@ private:
return false;
LowLevelILInstruction addOperand = add.GetSourceExpr<LLIL_SET_REG>();
+ if (addOperand.operation == LLIL_SX)
+ addOperand = addOperand.GetSourceExpr<LLIL_SX>();
+ if (addOperand.operation == LLIL_ZX)
+ addOperand = addOperand.GetSourceExpr<LLIL_ZX>();
+
if (addOperand.operation == LLIL_ADD)
{
LowLevelILInstruction addLeftOperand = addOperand.GetLeftExpr<LLIL_ADD>();
@@ -3083,7 +3095,7 @@ private:
if (addRightOperand.GetConstant() != (ldAddrRightOperandValue & 0xffffffff))
return false;
}
- else if ((addOperand.operation != LLIL_REG) || (addOperand.GetSourceRegister<LLIL_REG>() != pltReg)) //Simple assignment
+ else if ((addOperand.operation != LLIL_REG) || (addOperand.GetSourceRegister<LLIL_REG>() != pltReg)) // Simple assignment
return false;
LowLevelILInstruction jump = il->GetInstruction(3);
@@ -3094,9 +3106,14 @@ private:
if (jump.GetDestRegister<LLIL_SET_REG>() != pltReg)
return false;
LowLevelILInstruction luiOperand = jump.GetSourceExpr<LLIL_SET_REG>();
+ if (luiOperand.operation == LLIL_SX)
+ luiOperand = luiOperand.GetSourceExpr<LLIL_SX>();
+ if (luiOperand.operation == LLIL_ZX)
+ luiOperand = luiOperand.GetSourceExpr<LLIL_ZX>();
+
if (!LowLevelILFunction::IsConstantType(luiOperand.operation))
return false;
- if (luiOperand.size != func->GetArchitecture()->GetAddressSize())
+ if (luiOperand.size < 4)
return false;
if (((uint64_t) luiOperand.GetConstant()) != pltHi)
return false;
@@ -3219,9 +3236,15 @@ private:
if (lui.operation != LLIL_SET_REG)
return false;
LowLevelILInstruction luiOperand = lui.GetSourceExpr<LLIL_SET_REG>();
+ if (luiOperand.operation == LLIL_SX)
+ luiOperand = luiOperand.GetSourceExpr<LLIL_SX>();
+ if (luiOperand.operation == LLIL_ZX)
+ luiOperand = luiOperand.GetSourceExpr<LLIL_ZX>();
+
if (!LowLevelILFunction::IsConstantType(luiOperand.operation))
return false;
- if (luiOperand.size != func->GetArchitecture()->GetAddressSize())
+ /* mips64 is going to load this in two 32 bit halves so it shouldn't be address size */
+ if (luiOperand.size < 4)
return false;
uint64_t addrPastGot = luiOperand.GetConstant();
uint32_t pltReg = lui.GetDestRegister<LLIL_SET_REG>();
@@ -3254,7 +3277,7 @@ private:
ldAddrRightOperandValue = -ldAddrRightOperandValue;
entry = addrPastGot + ldAddrRightOperandValue;
}
- else if (ldAddrOperand.operation != LLIL_REG) //If theres no constant
+ else if (ldAddrOperand.operation != LLIL_REG) // If there's no constant
return false;
Ref<Symbol> sym = data->GetSymbolByAddress(entry);
@@ -3267,6 +3290,12 @@ private:
if (add.operation != LLIL_SET_REG)
return false;
LowLevelILInstruction addOperand = add.GetSourceExpr<LLIL_SET_REG>();
+ if(addOperand.operation == LLIL_SX) {
+ addOperand = addOperand.GetSourceExpr<LLIL_SX>();
+ }
+ if(addOperand.operation == LLIL_ZX) {
+ addOperand = addOperand.GetSourceExpr<LLIL_ZX>();
+ }
if (addOperand.operation == LLIL_ADD)
{
@@ -3281,7 +3310,7 @@ private:
if (addRightOperand.GetConstant() != ldAddrRightOperandValue)
return false;
}
- else if ((addOperand.operation != LLIL_REG) || (addOperand.GetSourceRegister<LLIL_REG>() != pltReg)) //Simple assignment
+ else if ((addOperand.operation != LLIL_REG) || (addOperand.GetSourceRegister<LLIL_REG>() != pltReg)) // Simple assignment
return false;
LowLevelILInstruction jump = il->GetInstruction(3);
@@ -3292,9 +3321,14 @@ private:
if (jump.GetDestRegister<LLIL_SET_REG>() != pltReg)
return false;
LowLevelILInstruction luiOperand = jump.GetSourceExpr<LLIL_SET_REG>();
+ if(luiOperand.operation == LLIL_SX)
+ luiOperand = luiOperand.GetSourceExpr<LLIL_SX>();
+ if(luiOperand.operation == LLIL_ZX)
+ luiOperand = luiOperand.GetSourceExpr<LLIL_ZX>();
+
if (!LowLevelILFunction::IsConstantType(luiOperand.operation))
return false;
- if (luiOperand.size != func->GetArchitecture()->GetAddressSize())
+ if (luiOperand.size < 4)
return false;
if (((uint64_t) luiOperand.GetConstant()) != addrPastGot)
return false;
@@ -3751,6 +3785,9 @@ extern "C"
mipseb->RegisterFunctionRecognizer(new MipsImportedFunctionRecognizer());
mips3->RegisterFunctionRecognizer(new MipsImportedFunctionRecognizer());
mips3el->RegisterFunctionRecognizer(new MipsImportedFunctionRecognizer());
+ mips64el->RegisterFunctionRecognizer(new MipsImportedFunctionRecognizer());
+ mips64eb->RegisterFunctionRecognizer(new MipsImportedFunctionRecognizer());
+ cnmips64eb->RegisterFunctionRecognizer(new MipsImportedFunctionRecognizer());
mipseb->RegisterRelocationHandler("ELF", new MipsElfRelocationHandler());
mipsel->RegisterRelocationHandler("ELF", new MipsElfRelocationHandler());
diff --git a/arch/powerpc/arch_ppc.cpp b/arch/powerpc/arch_ppc.cpp
index d806e0f6..ef6f7dc4 100644
--- a/arch/powerpc/arch_ppc.cpp
+++ b/arch/powerpc/arch_ppc.cpp
@@ -2293,6 +2293,11 @@ public:
{
}
+ virtual bool IsStackReservedForArgumentRegisters() override
+ {
+ return true;
+ }
+
virtual vector<uint32_t> GetIntegerArgumentRegisters() override
{
diff --git a/arch/powerpc/il.cpp b/arch/powerpc/il.cpp
index 46e672a6..043acf08 100644
--- a/arch/powerpc/il.cpp
+++ b/arch/powerpc/il.cpp
@@ -828,6 +828,16 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
il.FlagBit(4, IL_FLAG_SO_7, 0))))))))))))))))))))))))))))))))));
break;
+ case PPC_ID_MFSPR:
+ REQUIRE2OPS
+ il.AddInstruction(il.SetRegister(4, oper0->reg, il.Unimplemented()));
+ break;
+
+ case PPC_ID_MFMSR:
+ REQUIRE1OP
+ il.AddInstruction(il.SetRegister(4, oper0->reg, il.Unimplemented()));
+ break;
+
case PPC_ID_MCRF:
{
REQUIRE2OPS
@@ -1087,6 +1097,7 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
*/
case PPC_ID_LWZX:
case PPC_ID_LWZUX:
+ case PPC_ID_LWARX:
REQUIRE3OPS
ei0 = operToIL(il, oper1, OTI_GPR0_ZERO, PPC_IL_EXTRA_DEFAULT, addressSize_l); // d(rA) or 0
ei0 = il.Load(4, il.Add(addressSize_l, ei0, operToIL_a(il, oper2, addressSize_l))); // [d(rA) + d(rB)]
@@ -1458,6 +1469,7 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
/* store word indexed [with update] */
case PPC_ID_STWX:
+ case PPC_ID_STWCX:
case PPC_ID_STWUX: /* store(size, addr, val) */
REQUIRE3OPS
if (addressSize_l == 8)