| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-06-12 | Disassemble SFENCE.VM instruction | Mason Reed | |
| 2024-03-08 | Fix RISC-V CSRRW, CSRRS, and CSRRC instr disass | Pete Dietl | |
| Make the CSR instructions show the CSR 12-bit immediate operand as an unsigned integer. This is a special case of the I-instruction format, where it is same except that the 12-bit immediate is treated as unsigned rather than signed. | |||
| 2024-02-01 | RISC-V: Fix disassembly of compressed JAL instruction | Pete Dietl | |
| Change integer register involved via compressed JAL instruction from 0 (x0 (zero)) to 1 (x1 (ra)) | |||
| 2024-01-04 | Add RISC-V architecture plugin | Rusty Wagner | |
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index : public/binaryninja-api.git | |
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