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2024-04-10Update xed to v2024.04.01Xusheng
2024-04-09riscv : Remove uses of BnString per #5244KyleMiles
2024-04-08Fix lifting for movs* and stos* instructions.Brian Potchik
2024-03-26added lifting for EXTSW LD LDU LDUX LDX SLD SRAD SRADI SRD STD STDU STDUX STDXGalen Williamson
2024-03-25[arch-x86] improve lifting for *movd* and *movq* instructionsGalen Williamson
2024-03-22Remove FloatTruncate as its implied by 'FloatToInt'Peter LaFosse
2024-03-21Update to Rust 1.77Rusty Wagner
2024-03-20Implement Hash, PartialEq & Eq for riscv Registermason
2024-03-15Separate local variable tokens in higher level ILs from stack variable ↵Rusty Wagner
tokens in lower levels, and improve token usage in disassembly
2024-03-14Update to Rust 1.76Rusty Wagner
2024-03-12moved over from https://github.com/Vector35/arch-armv7/pull/81Galen Williamson
2024-03-08Fix RISC-V CSRRW, CSRRS, and CSRRC instr disassPete Dietl
Make the CSR instructions show the CSR 12-bit immediate operand as an unsigned integer. This is a special case of the I-instruction format, where it is same except that the 12-bit immediate is treated as unsigned rather than signed.
2024-03-08Fix X86_64_RELOC_UNSIGNED not handling external symbolsVisual Ehrmanntraut
Signed-off-by: Visual Ehrmanntraut <30368284+VisualEhrmanntraut@users.noreply.github.com>
2024-03-05Move architecture modules into the API repoRusty Wagner
2024-02-01RISC-V: Fix disassembly of compressed JAL instructionPete Dietl
Change integer register involved via compressed JAL instruction from 0 (x0 (zero)) to 1 (x1 (ra))
2024-01-04Add RISC-V relocations required by Linux kernel modulesRusty Wagner
2024-01-04Add RISC-V architecture pluginRusty Wagner