From 7c0514bb74642c87f0282e39c211befd3a20fc3c Mon Sep 17 00:00:00 2001
From: Mason Reed <mason@vector35.com>
Date: Wed, 12 Jun 2024 11:35:38 -0400
Subject: Disassemble SFENCE.VM instruction

---
 arch/riscv/disasm/src/lib.rs | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/riscv/disasm/src/lib.rs b/arch/riscv/disasm/src/lib.rs
index af7cd9a6..0703cd56 100644
--- a/arch/riscv/disasm/src/lib.rs
+++ b/arch/riscv/disasm/src/lib.rs
@@ -98,6 +98,7 @@ pub enum Op<D: RiscVDisassembler> {
     Sret,
     Mret,
     Wfi,
+    SfenceVm(RTypeIntInst<D>),
     SfenceVma(RTypeIntInst<D>),
 
     //
@@ -1867,6 +1868,7 @@ impl<D: RiscVDisassembler> Instr<D> {
                     ops.push(Operand::R(j.rd()));
                     ops.push(Operand::I(j.imm()));
                 }
+                Op::SfenceVm(ref r) => {}
                 Op::SfenceVma(ref r) => {
                     ops.push(Operand::R(r.rs1()));
                     ops.push(Operand::R(r.rs2()));
@@ -2077,6 +2079,7 @@ impl<'a, D: RiscVDisassembler + 'a> Mnem<'a, D> {
 
                 Op::Wfi => "wfi",
 
+                Op::SfenceVm(..) => "sfence.vm",
                 Op::SfenceVma(..) => "sfence.vma",
 
                 Op::Csrrw(..) => "csrrw",
@@ -3138,6 +3141,9 @@ pub trait RiscVDisassembler: Sized + Copy + Clone {
                                     f if (f & 0xfe0) == 0x120 => {
                                         Op::SfenceVma(RTypeIntInst::new(inst)?)
                                     }
+                                    0x104 => {
+                                        Op::SfenceVm(RTypeIntInst::new(inst)?)
+                                    }
 
                                     0x000 => Op::Ecall,
                                     0x001 => Op::Ebreak,
-- 
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