From d1cbe3f55e2b92b7acc0f9792ae6695153299f9c Mon Sep 17 00:00:00 2001 From: Pete Dietl Date: Wed, 31 Jan 2024 22:41:21 -0800 Subject: RISC-V: Fix disassembly of compressed JAL instruction Change integer register involved via compressed JAL instruction from 0 (x0 (zero)) to 1 (x1 (ra)) --- arch/riscv/disasm/src/lib.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/disasm/src/lib.rs b/arch/riscv/disasm/src/lib.rs index 6762bb5d..b9505724 100644 --- a/arch/riscv/disasm/src/lib.rs +++ b/arch/riscv/disasm/src/lib.rs @@ -2395,7 +2395,7 @@ pub trait RiscVDisassembler: Sized + Copy + Clone { } 0b001_01 if int_width == 4 => { // JAL - Op::Jal(JTypeInst::new(IntReg::new(0), inst.cj_imm())?) + Op::Jal(JTypeInst::new(IntReg::new(1), inst.cj_imm())?) } 0b001_01 => { // ADDIW -- cgit v1.3.1