From 1ec0d4fced11af730db0d9273fb512563fc02a0a Mon Sep 17 00:00:00 2001
From: Mark Rowe <mark@vector35.com>
Date: Sat, 18 Oct 2025 10:31:00 -0700
Subject: [AArch64] Lift FEAT_CSSC instructions

`abs`, `smax`, `smin`, `umax`, and `umin` are lifted to instruction
sequences involving comparisons, while `cnt` and `ctz` are lifted to
intrinsics.
---
 arch/arm64/arch_arm64.cpp | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'arch/arm64/arch_arm64.cpp')

diff --git a/arch/arm64/arch_arm64.cpp b/arch/arm64/arch_arm64.cpp
index 5faf37e5..2ec4a9f2 100644
--- a/arch/arm64/arch_arm64.cpp
+++ b/arch/arm64/arch_arm64.cpp
@@ -996,6 +996,10 @@ class Arm64Architecture : public Architecture
 			return "_eret";
 		case ARM64_INTRIN_CLZ:
 			return "_CountLeadingZeros";
+		case ARM64_INTRIN_CNT:
+			return "_PopulationCount";
+		case ARM64_INTRIN_CTZ:
+			return "_CountTrailingZeros";
 		case ARM64_INTRIN_CLREX:
 			return "__clrex";
 		case ARM64_INTRIN_REV:
@@ -1086,6 +1090,8 @@ class Arm64Architecture : public Architecture
 			};
 			break;
 		case ARM64_INTRIN_CLZ:        // reads <Xn>
+		case ARM64_INTRIN_CNT:        // reads <Xn>
+		case ARM64_INTRIN_CTZ:        // reads <Xn>
 		case ARM64_INTRIN_PRFM:
 		case ARM64_INTRIN_REV:   // reads <Xn>
 		case ARM64_INTRIN_RBIT:  // reads <Xn>
@@ -1149,6 +1155,8 @@ class Arm64Architecture : public Architecture
 		case ARM64_INTRIN_XPACD:      // writes <Xd>
 		case ARM64_INTRIN_XPACI:      // writes <Xd>
 		case ARM64_INTRIN_CLZ:        // writes <Xd>
+		case ARM64_INTRIN_CNT:        // writes <Xd>
+		case ARM64_INTRIN_CTZ:        // writes <Xd>
 		case ARM64_INTRIN_REV:        // writes <Xd>
 		case ARM64_INTRIN_RBIT:       // writes <Xd>
 			return {Type::IntegerType(8, false)};
-- 
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