From 6e1306923c60b3d6c1cefb1fcc240f1a064d6f20 Mon Sep 17 00:00:00 2001 From: Mark Rowe Date: Thu, 18 Sep 2025 11:46:39 -0700 Subject: [AArch64] Update disassembler based on 2025-06 ARM ISA data Alongside this I also added support for decoding: * LDR / STR (table) * PMULLB / PMULLT * ABS / CNT / CTZ * SMIN / SMAX / UMIN / UMAX * RPRFM * PSEL Note that while these instructions will now be disassembled, they are not yet lifted to LLIL. Additionally, I fixed a number of errors in the decoding of some less commonly occurring instructions. --- arch/arm64/disassembler/decode.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/disassembler/decode.c') diff --git a/arch/arm64/disassembler/decode.c b/arch/arm64/disassembler/decode.c index b444bbcd..99d8bba0 100644 --- a/arch/arm64/disassembler/decode.c +++ b/arch/arm64/disassembler/decode.c @@ -10,8 +10,8 @@ int aarch64_decompose(uint32_t instructionValue, Instruction* instr, uint64_t ad ctx.halted = 1; // enable disassembly of exception instructions like DCPS1 ctx.insword = instructionValue; ctx.address = address; - ctx.features0 = ARCH_FEATURES_ALL; - ctx.features1 = ARCH_FEATURES_ALL; + ARCH_FEATURES_ENABLE_ALL(ctx.decode_features); + ARCH_FEATURES_ENABLE_ALL(ctx.pcode_features); ctx.EDSCR_HDE = 1; /* have the spec-generated code populate all the pcode variables */ -- cgit v1.3.1