From 6e1306923c60b3d6c1cefb1fcc240f1a064d6f20 Mon Sep 17 00:00:00 2001 From: Mark Rowe Date: Thu, 18 Sep 2025 11:46:39 -0700 Subject: [AArch64] Update disassembler based on 2025-06 ARM ISA data Alongside this I also added support for decoding: * LDR / STR (table) * PMULLB / PMULLT * ABS / CNT / CTZ * SMIN / SMAX / UMIN / UMAX * RPRFM * PSEL Note that while these instructions will now be disassembled, they are not yet lifted to LLIL. Additionally, I fixed a number of errors in the decoding of some less commonly occurring instructions. --- arch/arm64/disassembler/sysregs_fmt_gen.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/disassembler/sysregs_fmt_gen.c') diff --git a/arch/arm64/disassembler/sysregs_fmt_gen.c b/arch/arm64/disassembler/sysregs_fmt_gen.c index 3a3a4767..4760d219 100644 --- a/arch/arm64/disassembler/sysregs_fmt_gen.c +++ b/arch/arm64/disassembler/sysregs_fmt_gen.c @@ -740,7 +740,7 @@ const char *get_system_register_name(enum SystemReg sr) case REG_CTR_EL0: return "ctr_el0"; case REG_DCZID_EL0: return "dczid_el0"; case REG_NZCV: return "nzcv"; - case REG_DAIF: return "daif"; + case REG_DAIF: return "daifset"; case REG_SVCR: return "svcr"; case REG_DIT: return "dit"; case REG_SSBS: return "ssbs"; @@ -1412,7 +1412,7 @@ const char *get_system_register_name(enum SystemReg sr) case REG_CNTPS_TVAL_EL1: return "cntps_tval_el1"; case REG_CNTPS_CTL_EL1: return "cntps_ctl_el1"; case REG_CNTPS_CVAL_EL1: return "cntps_cval_el1"; - case REG_PSTATE_SPSEL: return "pstate_spsel"; + case REG_PSTATE_SPSEL: return "spsel"; case REG_PWRDNSAVE0: return "pwrdnsave0"; case REG_NRG_ACC_CTL: return "nrg_acc_ctl"; case REG_AON_CNT0: return "aon_cnt0"; -- cgit v1.3.1