From 6e1306923c60b3d6c1cefb1fcc240f1a064d6f20 Mon Sep 17 00:00:00 2001 From: Mark Rowe Date: Thu, 18 Sep 2025 11:46:39 -0700 Subject: [AArch64] Update disassembler based on 2025-06 ARM ISA data Alongside this I also added support for decoding: * LDR / STR (table) * PMULLB / PMULLT * ABS / CNT / CTZ * SMIN / SMAX / UMIN / UMAX * RPRFM * PSEL Note that while these instructions will now be disassembled, they are not yet lifted to LLIL. Additionally, I fixed a number of errors in the decoding of some less commonly occurring instructions. --- arch/arm64/disassembler/sysregs_gen.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64/disassembler/sysregs_gen.h') diff --git a/arch/arm64/disassembler/sysregs_gen.h b/arch/arm64/disassembler/sysregs_gen.h index 54978f45..e971d317 100644 --- a/arch/arm64/disassembler/sysregs_gen.h +++ b/arch/arm64/disassembler/sysregs_gen.h @@ -3,7 +3,7 @@ #include -enum SystemReg +enum SystemReg { SYSREG_NONE=0, REG_EDSCR =4 /* 4 */, // S0_0_c0_c0_4 at min EL0: EDSCR -- cgit v1.3.1