From 9373cab26ee2e7b2febab7674360d54d6fb8adc6 Mon Sep 17 00:00:00 2001
From: Galen Williamson <galen@vector35.com>
Date: Tue, 4 Feb 2025 17:02:30 -0500
Subject: WIP improve thumb2 MSR lifting

---
 arch/armv7/thumb2_disasm/il_thumb2.cpp | 42 ++++++++++++++++++++++++++--------
 1 file changed, 33 insertions(+), 9 deletions(-)

(limited to 'arch/armv7/thumb2_disasm/il_thumb2.cpp')

diff --git a/arch/armv7/thumb2_disasm/il_thumb2.cpp b/arch/armv7/thumb2_disasm/il_thumb2.cpp
index 56443ff1..05a9f16f 100644
--- a/arch/armv7/thumb2_disasm/il_thumb2.cpp
+++ b/arch/armv7/thumb2_disasm/il_thumb2.cpp
@@ -1142,16 +1142,40 @@ bool GetLowLevelILForThumbInstruction(Architecture* arch, LowLevelILFunction& il
 		int intrinsic_id = ARMV7_INTRIN_MSR;
 
 		/* certain MSR scenarios earn a specialized intrinsic */
-		if (dest_reg == REGS_BASEPRI)
-			intrinsic_id = ARM_M_INTRIN_SET_BASEPRI;
+		// if (dest_reg == REGS_BASEPRI)
+		// 	intrinsic_id = ARM_M_INTRIN_SET_BASEPRI;
+		switch (dest_reg) {
+			case REGS_MSP:
+			case REGS_PSP:
+			case REGS_BASEPRI:
+			case REGS_BASEPRI_MAX:
+			case REGS_PRIMASK:
+			case REGS_FAULTMASK:
+			case REGS_CONTROL:
+			case REGS_IPSR:
+			case REGS_EPSR:
+			case REGS_IEPSR:
+				il.AddInstruction(
+					il.Intrinsic(
+						{}, /* outputs */
+						intrinsic_id,
+						{
+							il.Register(4, dest_reg),
+							ReadILOperand(il, instr, 1)
+						} /* inputs */
+					)
+				);
+				break;
+			default:
+				il.AddInstruction(
+					il.Intrinsic(
+						{RegisterOrFlag::Register(dest_reg)}, /* outputs */
+						intrinsic_id,
+						{ReadILOperand(il, instr, 1)} /* inputs */
+					)
+				);
+		}
 
-		il.AddInstruction(
-			il.Intrinsic(
-				{RegisterOrFlag::Register(dest_reg)}, /* outputs */
-				intrinsic_id,
-				{ReadILOperand(il, instr, 1)} /* inputs */
-			)
-		);
 		break;
 	}
 	case armv7::ARMV7_MUL:
-- 
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