From d6e13c753b30260b182cfe433e4e275244a4ab78 Mon Sep 17 00:00:00 2001 From: Galen Williamson Date: Wed, 23 Jul 2025 13:56:24 -0400 Subject: [armv7/thumb2] Fix Lifting for PC-relative vldr instruction does not align PC when calculating address #6947 Updated thumb2 pcode parser used by disassembler generator to use Tatsu instead of deprecated Grako --- arch/armv7/thumb2_disasm/spec.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/armv7/thumb2_disasm/spec.cpp') diff --git a/arch/armv7/thumb2_disasm/spec.cpp b/arch/armv7/thumb2_disasm/spec.cpp index 89ee1807..f618eff7 100644 --- a/arch/armv7/thumb2_disasm/spec.cpp +++ b/arch/armv7/thumb2_disasm/spec.cpp @@ -34446,8 +34446,8 @@ int vcvt_float_int(struct decomp_request *req, struct decomp_result *res) /* pcode: dp_operation = (sz == 1) */ res->fields[FIELD_dp_operation] = ((res->fields[FIELD_sz]) == (1)); res->fields_mask[FIELD_dp_operation >> 6] |= 1LL << (FIELD_dp_operation & 63); - /* pcode: unsigned = (op == '0') */ - res->fields[FIELD_unsigned] = ((res->fields[FIELD_op]) == (0x0)); + /* pcode: unsigned = (opc3 == '0') */ + res->fields[FIELD_unsigned] = ((res->fields[FIELD_opc3]) == (0x0)); res->fields_mask[FIELD_unsigned >> 6] |= 1LL << (FIELD_unsigned & 63); /* pcode: m = UInt(Vm:M) */ res->fields[FIELD_m] = ((res->fields[FIELD_Vm]<fields[FIELD_M])); -- cgit v1.3.1