From c6623fa5f2682f506d2d399d1b12547a195565f7 Mon Sep 17 00:00:00 2001 From: noone Date: Wed, 31 Jul 2024 22:48:31 -0500 Subject: Add decode, disassembly, IL for TLBINV, TLBINVF --- arch/mips/il.cpp | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/mips/il.cpp') diff --git a/arch/mips/il.cpp b/arch/mips/il.cpp index d5bc1421..f14a8d3c 100644 --- a/arch/mips/il.cpp +++ b/arch/mips/il.cpp @@ -1876,6 +1876,18 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu })); break; + case MIPS_TLBINV: + il.AddInstruction(il.Intrinsic({}, MIPS_INTRIN_TLBINV, { + il.Register(registerSize, REG_INDEX), + il.Register(registerSize, REG_ENTRY_HI) + })); + break; + + case MIPS_TLBINVF: + il.AddInstruction(il.Intrinsic({}, MIPS_INTRIN_TLBINVF, { + il.Register(registerSize, REG_INDEX), + })); + break; case CNMIPS_BADDU: il.AddInstruction(SetRegisterOrNop(il, 8, registerSize, op1.reg, -- cgit v1.3.1