From a542d0c9cd33fed5919c3cd9d598bb8d1a300ae8 Mon Sep 17 00:00:00 2001 From: Pete Dietl Date: Sun, 18 Feb 2024 13:58:38 -0800 Subject: Fix RISC-V CSRRW, CSRRS, and CSRRC instr disass Make the CSR instructions show the CSR 12-bit immediate operand as an unsigned integer. This is a special case of the I-instruction format, where it is same except that the 12-bit immediate is treated as unsigned rather than signed. --- arch/riscv/src/lib.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/riscv/src/lib.rs') diff --git a/arch/riscv/src/lib.rs b/arch/riscv/src/lib.rs index d8f6cff5..8b9fde31 100644 --- a/arch/riscv/src/lib.rs +++ b/arch/riscv/src/lib.rs @@ -1314,7 +1314,7 @@ impl architecture::Architecture fo Op::Csrrw(i) => { let rd = Register::from(i.rd()); let rs1 = Liftable::lift(il, Register::from(i.rs1())); - let csr = il.const_int(4, i.imm() as u64); + let csr = il.const_int(4, i.csr() as u64); if i.rd().id() == 0 { il.intrinsic(Lifter::::NO_OUTPUTS, Intrinsic::Csrwr, [csr, rs1]) @@ -1326,7 +1326,7 @@ impl architecture::Architecture fo Op::Csrrs(i) => { let rd = Register::from(i.rd()); let rs1 = Liftable::lift(il, Register::from(i.rs1())); - let csr = il.const_int(4, i.imm() as u64); + let csr = il.const_int(4, i.csr() as u64); if i.rs1().id() == 0 { il.intrinsic([rd], Intrinsic::Csrrd, [csr]).append(); @@ -1337,7 +1337,7 @@ impl architecture::Architecture fo Op::Csrrc(i) => { let rd = Register::from(i.rd()); let rs1 = Liftable::lift(il, Register::from(i.rs1())); - let csr = il.const_int(4, i.imm() as u64); + let csr = il.const_int(4, i.csr() as u64); if i.rs1().id() == 0 { il.intrinsic([rd], Intrinsic::Csrrd, [csr]).append(); -- cgit v1.3.1