From 193450bcf90800753aec316322ee651c5520ea57 Mon Sep 17 00:00:00 2001 From: Galen Williamson Date: Wed, 6 Aug 2025 19:22:13 -0400 Subject: [armv7] Add lifting for VCVT floating-point scalar variants --- arch/armv7/il.cpp | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/armv7/il.cpp b/arch/armv7/il.cpp index de53689b..73cf9a9a 100644 --- a/arch/armv7/il.cpp +++ b/arch/armv7/il.cpp @@ -4936,18 +4936,31 @@ bool GetLowLevelILForArmInstruction(Architecture* arch, uint64_t addr, LowLevelI case ARMV7_VCVT: switch (instr.dataType) { + // To integer cases case DT_S32: case DT_U32: switch (instr.dataType2) { case DT_F32: case DT_F64: - // ConditionExecute(il, instr.cond, - // il.SetRegister(get_register_size(op1.reg), op1.reg, - // il.FloatToInt(4, il.Register(get_register_size(op2.reg), op2.reg)))); - ConditionExecute(il, instr.cond, - il.SetRegister(get_register_size(op1.reg), op1.reg, - il.FloatToInt(get_register_size(op1.reg), il.Register(get_register_size(op2.reg), op2.reg)))); + ConditionExecute(il, instr.cond, il.SetRegister(get_register_size(op1.reg), op1.reg, + il.FloatToInt(get_register_size(op1.reg), il.RoundToInt(get_register_size(op2.reg), + il.Register(get_register_size(op2.reg), op2.reg))))); + break; + default: + break; + } + break; + // To float from integer cases + case DT_F32: + case DT_F64: + switch (instr.dataType2) + { + case DT_S32: + case DT_U32: + ConditionExecute(il, instr.cond, il.SetRegister(get_register_size(op1.reg), op1.reg, + il.IntToFloat(get_register_size(op1.reg), + il.Register(get_register_size(op2.reg), op2.reg)))); break; default: break; -- cgit v1.3.1