From 7b816fc2e285aa9cd77fba33bc55afa16947095f Mon Sep 17 00:00:00 2001 From: KyleMiles Date: Thu, 1 Jun 2023 17:36:20 -0400 Subject: Add Var, SSAVar, and AliasedVar to commonil.py, and update the relavent MLIL/HLIL instrutctions --- python/commonil.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'python/commonil.py') diff --git a/python/commonil.py b/python/commonil.py index f84da073..288db8d9 100644 --- a/python/commonil.py +++ b/python/commonil.py @@ -189,3 +189,18 @@ class SetReg: @dataclass(frozen=True, repr=False, eq=False) class Intrinsic(BaseILInstruction): pass + + +@dataclass(frozen=True, repr=False, eq=False) +class VariableInstruction(BaseILInstruction): + pass + + +@dataclass(frozen=True, repr=False, eq=False) +class SSAVariableInstruction(SSA, VariableInstruction): + pass + + +@dataclass(frozen=True, repr=False, eq=False) +class AliasedVariableInstruction(VariableInstruction): + pass -- cgit v1.3.1