From e7d9bb894f35b4f80d4f626d0f8348a800f3fe51 Mon Sep 17 00:00:00 2001
From: Peter LaFosse <peter@vector35.com>
Date: Fri, 5 Nov 2021 13:18:09 -0400
Subject: Fix vars_written/vars_read/vars_address_taken

---
 python/lowlevelil.py | 25 +++++++------------------
 1 file changed, 7 insertions(+), 18 deletions(-)

(limited to 'python/lowlevelil.py')

diff --git a/python/lowlevelil.py b/python/lowlevelil.py
index a301dc2a..313feec4 100644
--- a/python/lowlevelil.py
+++ b/python/lowlevelil.py
@@ -1936,18 +1936,7 @@ class LowLevelILFlag_cond(LowLevelILInstruction):
 
 @dataclass(frozen=True, repr=False)
 class LowLevelILAdd_overflow(LowLevelILBinaryBase, Arithmetic):
-
-	@property
-	def left(self) -> LowLevelILInstruction:
-		return self.get_expr(0)
-
-	@property
-	def right(self) -> LowLevelILInstruction:
-		return self.get_expr(1)
-
-	@property
-	def operands(self) -> List[LowLevelILOperandType]:
-		return [self.left, self.right]
+	pass
 
 
 @dataclass(frozen=True, repr=False)
@@ -4686,13 +4675,13 @@ class LowLevelILBasicBlock(basicblock.BasicBlock):
 		return self._il_function
 
 
-def LLIL_TEMP(n:int) -> int:
-	return n | 0x80000000
+def LLIL_TEMP(n:Union[ILRegister, int]) -> int:
+	return int(n) | 0x80000000
 
 
-def LLIL_REG_IS_TEMP(n:int) -> bool:
-	return (n & 0x80000000) != 0
+def LLIL_REG_IS_TEMP(n:Union[ILRegister, int]) -> bool:
+	return (int(n) & 0x80000000) != 0
 
 
-def LLIL_GET_TEMP_REG_INDEX(n:int) -> int:
-	return n & 0x7fffffff
+def LLIL_GET_TEMP_REG_INDEX(n:Union[ILRegister, int]) -> int:
+	return int(n) & 0x7fffffff
-- 
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