From d3140edec185f47235b9e4642bdd56d6c585a341 Mon Sep 17 00:00:00 2001
From: Ryan Snyder <ryan@vector35.com>
Date: Thu, 21 Jan 2021 18:27:48 +0000
Subject: This is a combination of 23 commits, the work of Ryan Snyder:

Initial fresh repo

Add support for recent calling convention API updates and folds the binaryninjacore-sys crate directly into this one.

Add support for auto function analysis suppression

Finish moving binaryninjacore-sys back into this crate

Update for Symbol/Segment core API changes

Update for Symbol API cleanup

api: advance submodule reference, support Token changes

arch/lifting: support for flags in custom architectures

arch/lifting: support default flag write behaviors, handle more ops

build: enable headless binary support on MacOS via evil hack

bv: add BinaryView wrapper support, remove wrong comment

api: update to latest binja dev branch support

deps: bump dep versions

rust: bump to 2018 edition

api: bump to avoid cargo submodule brokenness

build: improve binaryninja path detection; enable linux linkhack

bv: stub for bv load settings

arch: fix flag related crash, minor llil update

api: update for recent changes

macos: disable linkhack briefly
---
 rust/src/llil/mod.rs | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 80 insertions(+)
 create mode 100644 rust/src/llil/mod.rs

(limited to 'rust/src/llil/mod.rs')

diff --git a/rust/src/llil/mod.rs b/rust/src/llil/mod.rs
new file mode 100644
index 00000000..c3b1b350
--- /dev/null
+++ b/rust/src/llil/mod.rs
@@ -0,0 +1,80 @@
+use std::fmt;
+
+// TODO provide some way to forbid emitting register reads for certain registers
+// also writing for certain registers (e.g. zero register must prohibit il.set_reg and il.reg
+// (replace with nop or const(0) respectively)
+// requirements on load/store memory address sizes?
+// can reg/set_reg be used with sizes that differ from what is in BNRegisterInfo?
+
+use crate::architecture::Register as ArchReg;
+use crate::architecture::Architecture;
+use crate::function::Location;
+
+mod function;
+mod instruction;
+mod expression;
+mod lifting;
+mod block;
+pub mod operation;
+
+pub use self::function::*;
+pub use self::instruction::*;
+pub use self::expression::*;
+pub use self::lifting::{Liftable, LiftableWithSize, Label, ExpressionBuilder, FlagWriteOp, RegisterOrConstant};
+pub use self::lifting::get_default_flag_write_llil;
+pub use self::lifting::get_default_flag_cond_llil;
+
+pub use self::block::Block as LowLevelBlock;
+pub use self::block::BlockIter as LowLevelBlockIter;
+
+pub type Lifter<Arch> = Function<Arch, Mutable, NonSSA<LiftedNonSSA>>;
+pub type LiftedFunction<Arch> = Function<Arch, Finalized, NonSSA<LiftedNonSSA>>;
+pub type LiftedExpr<'a, Arch> = Expression<'a, Arch, Mutable, NonSSA<LiftedNonSSA>, ValueExpr>;
+pub type RegularFunction<Arch> = Function<Arch, Finalized, NonSSA<RegularNonSSA>>;
+pub type SSAFunction<Arch> = Function<Arch, Finalized, SSA>;
+
+#[derive(Copy, Clone)]
+pub enum Register<R: ArchReg> {
+    ArchReg(R),
+    Temp(u32),
+}
+
+impl<R: ArchReg> Register<R> {
+    fn id(&self) -> u32 {
+        match *self {
+            Register::ArchReg(ref r) => r.id(),
+            Register::Temp(id) => 0x8000_0000 | id,
+        }
+    }
+}
+
+impl<R: ArchReg> fmt::Debug for Register<R> {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        match *self {
+            Register::ArchReg(ref r) => write!(f, "{}", r.name().as_ref()),
+            Register::Temp(id) => write!(f, "temp{}", id),
+        }
+    }
+}
+
+#[derive(Copy, Clone, Debug)]
+pub enum SSARegister<R: ArchReg> {
+    Full(Register<R>, u32), // no such thing as partial access to a temp register, I think
+    Partial(R, u32, R), // partial accesses only possible for arch registers, I think
+}
+
+impl<R: ArchReg> SSARegister<R> {
+    pub fn version(&self) -> u32 {
+        match *self {
+            SSARegister::Full(_, ver) |
+            SSARegister::Partial(_, ver, _) => ver
+        }
+    }
+}
+
+pub enum VisitorAction {
+    Descend,
+    Sibling,
+    Halt,
+}
+
-- 
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