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| author | Mason Reed <mason@vector35.com> | 2024-08-21 10:15:56 -0400 |
|---|---|---|
| committer | Mason Reed <mason@vector35.com> | 2024-08-21 18:52:04 -0400 |
| commit | 183a842161b08fe51c92cf7cef5b11ba3d1f03fa (patch) | |
| tree | a6f52655b8236d6dda58ed01be570ac96251d749 | |
| parent | 63f5f43ce24cee1e65df1caba02eb700c0ead443 (diff) | |
Fix thumb2 lifting of REV
| -rwxr-xr-x | arch/armv7/test_lift.py | 4 | ||||
| -rw-r--r-- | arch/armv7/thumb2_disasm/il_thumb2.cpp | 6 |
2 files changed, 6 insertions, 4 deletions
diff --git a/arch/armv7/test_lift.py b/arch/armv7/test_lift.py index ab97d1d9..96a6f4d9 100755 --- a/arch/armv7/test_lift.py +++ b/arch/armv7/test_lift.py @@ -122,7 +122,9 @@ test_cases = \ ('T', b'\x41\xf3\x41\x00', 'LLIL_SET_REG.d(r0,LLIL_ASR.d(LLIL_LSL.d(LLIL_REG.d(r1),LLIL_CONST.b(0x1D)),LLIL_CONST.b(0x1E)))'), # sbfx r0, r1, 20, 30 (starting at b20, width 30... gets clamped, so b31b30...b20 # just r0 = r1 >> 20, no left shift required - ('T', b'\x41\xf3\x1d\x50', 'LLIL_SET_REG.d(r0,LLIL_ASR.d(LLIL_REG.d(r1),LLIL_CONST.b(0x14)))') + ('T', b'\x41\xf3\x1d\x50', 'LLIL_SET_REG.d(r0,LLIL_ASR.d(LLIL_REG.d(r1),LLIL_CONST.b(0x14)))'), + # rev r1, r1 + ('T', b'\x09\xba', 'LLIL_SET_REG.d(r1,LLIL_OR.d(LLIL_LSR.d(LLIL_REG.d(r1),LLIL_CONST.d(0x18)),LLIL_OR.d(LLIL_LSL.d(LLIL_AND.d(LLIL_LSR.d(LLIL_REG.d(r1),LLIL_CONST.d(0x10)),LLIL_CONST.d(0xFF)),LLIL_CONST.d(0x8)),LLIL_OR.d(LLIL_LSL.d(LLIL_AND.d(LLIL_LSR.d(LLIL_REG.d(r1),LLIL_CONST.d(0x8)),LLIL_CONST.d(0xFF)),LLIL_CONST.d(0x10)),LLIL_LSL.d(LLIL_AND.d(LLIL_REG.d(r1),LLIL_CONST.d(0xFF)),LLIL_CONST.d(0x18))))))'), ] import re diff --git a/arch/armv7/thumb2_disasm/il_thumb2.cpp b/arch/armv7/thumb2_disasm/il_thumb2.cpp index f92060f9..aec37ed1 100644 --- a/arch/armv7/thumb2_disasm/il_thumb2.cpp +++ b/arch/armv7/thumb2_disasm/il_thumb2.cpp @@ -1033,9 +1033,9 @@ bool GetLowLevelILForThumbInstruction(Architecture* arch, LowLevelILFunction& il case armv7::ARMV7_REV: il.AddInstruction(WriteILOperand(il, instr, 0, il.Or(4, il.LogicalShiftRight(4, ReadILOperand(il, instr, 1), il.Const(4, 24)), - il.Or(4, il.And(4, il.LogicalShiftRight(4, ReadILOperand(il, instr, 1), il.Const(4, 16)), il.Const(4, 0xff)), - il.Or(4, il.And(4, il.LogicalShiftRight(4, ReadILOperand(il, instr, 1), il.Const(4, 8)), il.Const(4, 0xff)), - il.And(4, ReadILOperand(il, instr, 1), il.Const(4, 0xff))))))); + il.Or(4, il.ShiftLeft(4, il.And(4, il.LogicalShiftRight(4, ReadILOperand(il, instr, 1), il.Const(4, 16)), il.Const(4, 0xff)), il.Const(1, 8)), + il.Or(4, il.ShiftLeft(4, il.And(4, il.LogicalShiftRight(4, ReadILOperand(il, instr, 1), il.Const(4, 8)), il.Const(4, 0xff)), il.Const(1, 16)), + il.ShiftLeft(4, il.And(4, ReadILOperand(il, instr, 1), il.Const(4, 0xff)), il.Const(1, 24))))))); break; case armv7::ARMV7_REV16: il.AddInstruction(il.SetRegister(2, LLIL_TEMP(0), il.RotateRight(2, il.LowPart(2, ReadILOperand(il, instr, 1)), il.Const(1, 16)))); |