diff options
| author | Mason Reed <mason@vector35.com> | 2024-08-23 14:26:32 -0400 |
|---|---|---|
| committer | mason <35282038+emesare@users.noreply.github.com> | 2024-08-27 11:16:59 -0700 |
| commit | 2cd4df1784bc1eaabf1446d8355487e17f9bceae (patch) | |
| tree | 4f1a33b13883d1252de466cc6ebf061f21687d5d | |
| parent | 19d431815793d1a6e48d6c277d32a583047638a8 (diff) | |
Fix VDIV constraints and lift VNEG
| -rw-r--r-- | arch/armv7/thumb2_disasm/il_thumb2.cpp | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/arch/armv7/thumb2_disasm/il_thumb2.cpp b/arch/armv7/thumb2_disasm/il_thumb2.cpp index 996b76a3..539fa2cd 100644 --- a/arch/armv7/thumb2_disasm/il_thumb2.cpp +++ b/arch/armv7/thumb2_disasm/il_thumb2.cpp @@ -1553,9 +1553,27 @@ bool GetLowLevelILForNEONInstruction(Architecture* arch, LowLevelILFunction& il, } break; case armv7::ARMV7_VDIV: - il.AddInstruction(WriteArithOperand( - il, instr, il.FloatDiv(GetRegisterSize(instr, 0), ReadILOperand(il, instr, 1), - ReadILOperand(il, instr, 2)))); + if (strcmp(instr->format->operation, "vdiv.f64") == 0 || strcmp(instr->format->operation, "vdiv.f32") == 0) + { + il.AddInstruction(WriteArithOperand( + il, instr, il.FloatDiv(GetRegisterSize(instr, 0), ReadILOperand(il, instr, 1), + ReadILOperand(il, instr, 2)))); + } + else + { + il.AddInstruction(il.Unimplemented()); + } + break; + case armv7::ARMV7_VNEG: + if (strcmp(instr->format->operation, "vneg.f64") == 0 || strcmp(instr->format->operation, "vneg.f32") == 0) + { + il.AddInstruction(WriteArithOperand( + il, instr, il.FloatNeg(GetRegisterSize(instr, 0), ReadILOperand(il, instr, 1)))); + } + else + { + il.AddInstruction(il.Unimplemented()); + } break; case armv7::ARMV7_VMRS: // TODO: If this sets the apsr register we do not track that in the core flag group. |