[arm64] cleaned up dangling else warnings and removed unneeded ENC_LDR_Q* case from neon_intrinsics.cpp

1 files changed, 20 insertions, 9 deletions

diff --git a/arch/arm64/neon_intrinsics.cpp b/arch/arm64/neon_intrinsics.cpp
index 84a4a146..e8a45503 100644
--- a/arch/arm64/neon_intrinsics.cpp
+++ b/arch/arm64/neon_intrinsics.cpp
@@ -19770,11 +19770,6 @@ bool NeonGetLowLevelILForInstruction(
 		add_input_lane(inputs, il, instr.operands[1]);
 		add_output_reg(outputs, il, instr.operands[0]);
 		break;
-	case ENC_LDR_Q_LOADLIT:
-		intrin_id = ARM64_INTRIN_VLDRQ_P128;  // LDR Qd,[Xn]
-		add_input_reg(inputs, il, instr.operands[1]);
-		add_output_reg(outputs, il, instr.operands[0]);
-		break;
 	case ENC_LD2_ASISDLSE_R2:
 		if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
 			intrin_id = ARM64_INTRIN_VLD2Q_S8;
@@ -22892,15 +22887,19 @@ bool NeonGetLowLevelILForInstruction(
 	case ENC_TBL_ASIMDTBL_L1_1:
 	case ENC_TBX_ASIMDTBL_L1_1:
 		if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
+		{
 			if (instr.encoding == ENC_TBL_ASIMDTBL_L1_1)
 				intrin_id = ARM64_INTRIN_VTBL1_S8;  // TBL Vd.8B,{Vn.16B},Vm.8B
 			else
 				intrin_id = ARM64_INTRIN_VTBX1_S8;  // TBX Vd.8B,{Vn.16B},Vm.8B
+		}
 		else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+		{
 			if (instr.encoding == ENC_TBL_ASIMDTBL_L1_1)
 				intrin_id = ARM64_INTRIN_VQTBL1Q_S8;  // TBL Vd.16B,{Vn.16B},Vm.16B
 			else
 				intrin_id = ARM64_INTRIN_VQTBX1Q_S8;  // TBX Vd.16B,{Vn.16B},Vm.16B
+		}
 		add_input_reg(inputs, il, instr.operands[1]);
 		add_input_reg(inputs, il, instr.operands[2]);
 		add_output_reg(outputs, il, instr.operands[0]);
@@ -22911,19 +22910,23 @@ bool NeonGetLowLevelILForInstruction(
 	case ENC_TBX_ASIMDTBL_L2_2:
 	{
 		if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
+		{
 			if (instr.encoding == ENC_TBL_ASIMDTBL_L2_2)
 				intrin_id = ARM64_INTRIN_VTBL2_S8;  // TBL Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
 			else
 				intrin_id = ARM64_INTRIN_VTBX2_S8;  // TBX Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+		}
 		else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+		{
 			if (instr.encoding == ENC_TBL_ASIMDTBL_L2_2)
 				intrin_id = ARM64_INTRIN_VQTBL2Q_S8;  // TBL Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
 			else
 				intrin_id = ARM64_INTRIN_VQTBX2Q_S8;  // TBX Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
-		InstructionOperand tmp;
+		}
+		add_input_reg(inputs, il, instr.operands[1]);
+		InstructionOperand tmp(instr.operands[1]);
 		tmp.reg[0] = (Register) (instr.operands[1].reg[0] + 1);
 		add_input_reg(inputs, il, tmp);
-		add_input_reg(inputs, il, instr.operands[1]);
 		add_input_reg(inputs, il, instr.operands[2]);
 		add_output_reg(outputs, il, instr.operands[0]);
 		break;
@@ -22932,17 +22935,21 @@ bool NeonGetLowLevelILForInstruction(
 	case ENC_TBX_ASIMDTBL_L3_3:
 	{
 		if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
+		{
 			if (instr.encoding == ENC_TBL_ASIMDTBL_L3_3)
 				intrin_id = ARM64_INTRIN_VTBL3_S8;  // TBL Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
 			else
 				intrin_id = ARM64_INTRIN_VTBX3_S8;  // TBX Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+		}
 		else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+		{
 			if (instr.encoding == ENC_TBL_ASIMDTBL_L3_3)
 				intrin_id = ARM64_INTRIN_VQTBL3Q_S8;  // TBL Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
 			else
 				intrin_id = ARM64_INTRIN_VQTBX3Q_S8;  // TBX Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+		}
 		add_input_reg(inputs, il, instr.operands[1]);
-		InstructionOperand tmp;
+		InstructionOperand tmp(instr.operands[1]);
 		tmp.reg[0] = (Register) (instr.operands[1].reg[0] + 1);
 		add_input_reg(inputs, il, tmp);
 		tmp.reg[0] = (Register) (instr.operands[1].reg[0] + 2);
@@ -22955,17 +22962,21 @@ bool NeonGetLowLevelILForInstruction(
 	case ENC_TBX_ASIMDTBL_L4_4:
 	{
 		if (instr.operands[0].arrSpec == ARRSPEC_8BYTES)
+		{
 			if (instr.encoding == ENC_TBL_ASIMDTBL_L4_4)
 				intrin_id = ARM64_INTRIN_VTBL4_S8;  // TBL Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
 			else
 				intrin_id = ARM64_INTRIN_VTBX4_S8;  // TBX Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+		}
 		else if (instr.operands[0].arrSpec == ARRSPEC_16BYTES)
+		{
 			if (instr.encoding == ENC_TBL_ASIMDTBL_L4_4)
 				intrin_id = ARM64_INTRIN_VQTBL4Q_S8;  // TBL Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
 			else
 				intrin_id = ARM64_INTRIN_VQTBX4Q_S8;  // TBX Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+		}
 		add_input_reg(inputs, il, instr.operands[1]);
-		InstructionOperand tmp;
+		InstructionOperand tmp(instr.operands[1]);
 		tmp.reg[0] = (Register) (instr.operands[1].reg[0] + 1);
 		add_input_reg(inputs, il, tmp);
 		tmp.reg[0] = (Register) (instr.operands[1].reg[0] + 2);