[mips] Fix decoding of MIPS ds*32 instructions, add lifting for MIPS drotr* instructions; clean up some warnings in powerpc/il.cpp

3 files changed, 41 insertions, 11 deletions

diff --git a/arch/mips/il.cpp b/arch/mips/il.cpp
index f14a8d3c..97761e82 100644
--- a/arch/mips/il.cpp
+++ b/arch/mips/il.cpp
@@ -1513,22 +1513,28 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu
 		case MIPS_SLLV:
 			il.AddInstruction(SetRegisterOrNop(il, 4, registerSize, op1.reg, il.ShiftLeft(4, ReadILOperand(il, instr, 2, registerSize), il.And(4, ReadILOperand(il, instr, 3, registerSize), il.Const(4, 0x1f)))));
 			break;
-		case MIPS_DSLL:
 		case MIPS_DSLL32:
+			op3.immediate += 32;
+			// fall through
+		case MIPS_DSLL:
 			il.AddInstruction(SetRegisterOrNop(il, 8, registerSize, op1.reg, il.ShiftLeft(8, ReadILOperand(il, instr, 2, registerSize), ReadILOperand(il, instr, 3, registerSize))));
 			break;
 		case MIPS_DSLLV:
 			il.AddInstruction(SetRegisterOrNop(il, 8, registerSize, op1.reg, il.ShiftLeft(8, ReadILOperand(il, instr, 2, registerSize), il.And(8, ReadILOperand(il, instr, 3, registerSize), il.Const(8, 0x3f)))));
 			break;
-		case MIPS_DSRL:
 		case MIPS_DSRL32:
+			op3.immediate += 32;
+			// fall through
+		case MIPS_DSRL:
 			il.AddInstruction(SetRegisterOrNop(il, 8, registerSize, op1.reg, il.LogicalShiftRight(8, ReadILOperand(il, instr, 2, registerSize), ReadILOperand(il, instr, 3, registerSize))));
 			break;
 		case MIPS_DSRLV:
 			il.AddInstruction(SetRegisterOrNop(il, 8, registerSize, op1.reg, il.LogicalShiftRight(8, ReadILOperand(il, instr, 2, registerSize), il.And(8, ReadILOperand(il, instr, 3, registerSize), il.Const(8, 0x3f)))));
 			break;
-		case MIPS_DSRA:
 		case MIPS_DSRA32:
+			op3.immediate += 32;
+			// fall through
+		case MIPS_DSRA:
 			il.AddInstruction(SetRegisterOrNop(il, 8, registerSize, op1.reg, il.ArithShiftRight(8, ReadILOperand(il, instr, 2, registerSize), ReadILOperand(il, instr, 3, registerSize))));
 			break;
 		case MIPS_DSRAV:
@@ -1598,6 +1604,13 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu
 
 			SignExtendHiLo(il, registerSize);
 			break;
+		case MIPS_DROTR32:
+			op3.immediate += 32;
+			// fall through
+		case MIPS_DROTR:
+		case MIPS_DROTRV:
+			il.AddInstruction(SetRegisterOrNop(il, 8, registerSize, op1.reg, il.RotateRight(8, ReadILOperand(il, instr, 2, registerSize), ReadILOperand(il, instr, 3, registerSize))));
+			break;
 		case MIPS_ROTR:
 		case MIPS_ROTRV:
 			il.AddInstruction(SetRegisterOrNop(il, 4, registerSize, op1.reg, il.RotateRight(4, ReadILOperand(il, instr, 2, registerSize), ReadILOperand(il, instr, 3, registerSize))));
@@ -2184,12 +2197,29 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu
 		case MIPS_PREFX:
 		case MIPS_WRPGPR:
 		case MIPS_RDPGPR:
+		case MIPS_SUXC1:
+		case MIPS_SWXC1:
+		// Floating point instructions
+		case MIPS_RSQRT_D:
+		case MIPS_RSQRT_S:
+		case MIPS_RSQRT:
+		case MIPS_RSQRT1:
+		case MIPS_RSQRT2:
 		case MIPS_RECIP1:
 		case MIPS_RECIP2:
 		case MIPS_RECIP:
-		case MIPS_SUXC1:
-		case MIPS_SWXC1:
-			il.AddInstruction(il.Unimplemented());
+		case MIPS_NMADD_D:
+		case MIPS_NMADD_PS:
+		case MIPS_NMADD_S:
+		case MIPS_NMSUB_D:
+		case MIPS_NMSUB_PS:
+		case MIPS_NMSUB_S:
+		case MIPS_MADD_D:
+		case MIPS_MADD_PS:
+		case MIPS_MADD_S:
+		case MIPS_MADDF_D:
+		case MIPS_MADDF_S:
+		il.AddInstruction(il.Unimplemented());
 			break;
 
 		// instructions that are just internal placeholders for other
diff --git a/arch/mips/mips/mips.c b/arch/mips/mips/mips.c
index 32c58aa6..e046d795 100644
--- a/arch/mips/mips/mips.c
+++ b/arch/mips/mips/mips.c
@@ -2214,7 +2214,7 @@ uint32_t mips_decompose_instruction(
 		case MIPS_DSLL32:
 		case MIPS_DSRA32:
 		case MIPS_DSRL32:
-			INS_3(REG, ins.r.rd, REG, ins.r.rt, IMM, ins.r.sa+32)
+			INS_3(REG, ins.r.rd, REG, ins.r.rt, IMM, ins.r.sa)
 			if (ins.r.rs != 0)
 				return 1;
 			break;
diff --git a/arch/powerpc/il.cpp b/arch/powerpc/il.cpp
index 43a47064..28883e5a 100644
--- a/arch/powerpc/il.cpp
+++ b/arch/powerpc/il.cpp
@@ -489,7 +489,7 @@ static void loadstoreppcfs(LowLevelILFunction& il,
 	bool update=false
 	)
 {
-	ExprId tmp;
+	ExprId tmp = 0;
 	const int addrsz = 4;
 	// assume single
 	if (!load_store_sz)
@@ -539,8 +539,8 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 	uint32_t rawInsn = *(const uint32_t *) data;
 
 	// for ppc_ps
-	ppc_reg_bn gqr_l = (ppc_reg_bn)0;
-	int w_l = 0;
+	// ppc_reg_bn gqr_l = (ppc_reg_bn)0;
+	// int w_l = 0;
 
 	addressSize_l = arch->GetAddressSize();
 	if (!le)
@@ -615,7 +615,7 @@ bool GetLowLevelILForPPCInstruction(Architecture *arch, LowLevelILFunction &il,
 		//MYLOG("oper3: %p\n", oper3);
 	}
 
-	ExprId ei0, ei1, ei2;
+	ExprId ei0 = 0, ei1 = 0, ei2 = 0;
 
 	switch(insn->id) {
 		/* add