diff options
| author | Galen Williamson <galen@vector35.com> | 2025-08-13 19:17:06 -0400 |
|---|---|---|
| committer | Galen Williamson <galen@vector35.com> | 2025-08-14 14:06:49 -0400 |
| commit | 7d9f39f95d3d95a839db64347c5d2f4cabf788dd (patch) | |
| tree | 3fc0734b492778c79292df794d3818385c4065c6 | |
| parent | 0becd045c5e3e0997c30cb64f19fe21b2b3c421f (diff) | |
[armv7] add explicit signedness to conversions for scalar forms of VCVT
| -rw-r--r-- | arch/armv7/il.cpp | 26 |
1 files changed, 23 insertions, 3 deletions
diff --git a/arch/armv7/il.cpp b/arch/armv7/il.cpp index 73cf9a9a..0d79bcf6 100644 --- a/arch/armv7/il.cpp +++ b/arch/armv7/il.cpp @@ -4938,14 +4938,28 @@ bool GetLowLevelILForArmInstruction(Architecture* arch, uint64_t addr, LowLevelI { // To integer cases case DT_S32: + switch (instr.dataType2) + { + case DT_F32: + case DT_F64: + ConditionExecute(il, instr.cond, il.SetRegister(get_register_size(op1.reg), op1.reg, + il.SignExtend(get_register_size(op1.reg), + il.FloatToInt(get_register_size(op1.reg), il.RoundToInt(get_register_size(op2.reg), + il.Register(get_register_size(op2.reg), op2.reg)))))); + break; + default: + break; + } + break; case DT_U32: switch (instr.dataType2) { case DT_F32: case DT_F64: ConditionExecute(il, instr.cond, il.SetRegister(get_register_size(op1.reg), op1.reg, - il.FloatToInt(get_register_size(op1.reg), il.RoundToInt(get_register_size(op2.reg), - il.Register(get_register_size(op2.reg), op2.reg))))); + il.ZeroExtend(get_register_size(op1.reg), + il.FloatToInt(get_register_size(op1.reg), il.RoundToInt(get_register_size(op2.reg), + il.Register(get_register_size(op2.reg), op2.reg)))))); break; default: break; @@ -4957,10 +4971,16 @@ bool GetLowLevelILForArmInstruction(Architecture* arch, uint64_t addr, LowLevelI switch (instr.dataType2) { case DT_S32: + ConditionExecute(il, instr.cond, il.SetRegister(get_register_size(op1.reg), op1.reg, + il.IntToFloat(get_register_size(op1.reg), + il.SignExtend(get_register_size(op1.reg), + il.Register(get_register_size(op2.reg), op2.reg))))); + break; case DT_U32: ConditionExecute(il, instr.cond, il.SetRegister(get_register_size(op1.reg), op1.reg, il.IntToFloat(get_register_size(op1.reg), - il.Register(get_register_size(op2.reg), op2.reg)))); + il.ZeroExtend(get_register_size(op1.reg), + il.Register(get_register_size(op2.reg), op2.reg))))); break; default: break; |