diff options
| author | Josh Ferrell <josh@vector35.com> | 2025-03-06 11:01:48 -0500 |
|---|---|---|
| committer | Josh Ferrell <josh@vector35.com> | 2025-03-06 16:38:58 -0500 |
| commit | aaff6a6e366219c52a629729d741fff1711eeb7d (patch) | |
| tree | e5edf1fd76f470aead52851ba5a8c3ebb56eff3b | |
| parent | d59ee7f42ceb379dc107c6bca723b012b0c0e24a (diff) | |
ARMv7: update test_lift.py and test.py
| -rwxr-xr-x | arch/armv7/test.py | 4 | ||||
| -rwxr-xr-x | arch/armv7/test_lift.py | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/armv7/test.py b/arch/armv7/test.py index 9ffb040e..6a6d1fef 100755 --- a/arch/armv7/test.py +++ b/arch/armv7/test.py @@ -9,9 +9,9 @@ test_cases_arm = [ # r0 = (r1 & 0b11111111111111111111111111100011) | ((r1 & 0b111) << 2) (b'\x11\x01\xc4\xe7', 'LLIL_SET_REG(r0,LLIL_OR(LLIL_AND(LLIL_REG(r0),LLIL_CONST(4294967267)),LLIL_LSL(LLIL_AND(LLIL_REG(r1),LLIL_CONST(7)),LLIL_CONST(2))))'), # bfi r0, r1, #2, #3 # temp0 = r2*r3; r0=tmp0&0xFFFFFFFF; r1=tmp0>>32 ... LOGICAL shift since mul is unsigned - (b'\x92\x03\x81\xe0', 'LLIL_SET_REG(temp0,LLIL_MUL(LLIL_REG(r2),LLIL_REG(r3))); LLIL_SET_REG(r0,LLIL_LOW_PART(LLIL_REG(temp0))); LLIL_SET_REG(r1,LLIL_LSR(LLIL_REG(temp0),LLIL_CONST(32)))'), # umull r0, r1, r2, r3 + (b'\x92\x03\x81\xe0', 'LLIL_SET_REG_SPLIT(r1,r0,LLIL_MULU_DP(LLIL_REG(r2),LLIL_REG(r3)))'), # umull r0, r1, r2, r3 # same, but ARITHMETIC shift since mul is signed - (b'\x92\x03\xc1\xe0', 'LLIL_SET_REG(temp0,LLIL_MUL(LLIL_REG(r2),LLIL_REG(r3))); LLIL_SET_REG(r0,LLIL_LOW_PART(LLIL_REG(temp0))); LLIL_SET_REG(r1,LLIL_ASR(LLIL_REG(temp0),LLIL_CONST(32)))'), # smull r0, r1, r2, r3 + (b'\x92\x03\xc1\xe0', 'LLIL_SET_REG_SPLIT(r1,r0,LLIL_MULS_DP(LLIL_REG(r2),LLIL_REG(r3)))'), # smull r0, r1, r2, r3 # multiply and accumulate: mla r0, r1, r2, r3 lift to r0 = r3 + (r1 * r2) (b'\x91\x32\x20\xe0', 'LLIL_SET_REG(r0,LLIL_ADD(LLIL_REG(r3),LLIL_MUL(LLIL_REG(r1),LLIL_REG(r2))))'), # mla r0, r1, r2, r3 # multiply and subtract: mls r0, r1, r2, r3 lift to r0 = r3 - (r1 * r2) diff --git a/arch/armv7/test_lift.py b/arch/armv7/test_lift.py index 96a6f4d9..a3906fc6 100755 --- a/arch/armv7/test_lift.py +++ b/arch/armv7/test_lift.py @@ -124,7 +124,7 @@ test_cases = \ # just r0 = r1 >> 20, no left shift required ('T', b'\x41\xf3\x1d\x50', 'LLIL_SET_REG.d(r0,LLIL_ASR.d(LLIL_REG.d(r1),LLIL_CONST.b(0x14)))'), # rev r1, r1 - ('T', b'\x09\xba', 'LLIL_SET_REG.d(r1,LLIL_OR.d(LLIL_LSR.d(LLIL_REG.d(r1),LLIL_CONST.d(0x18)),LLIL_OR.d(LLIL_LSL.d(LLIL_AND.d(LLIL_LSR.d(LLIL_REG.d(r1),LLIL_CONST.d(0x10)),LLIL_CONST.d(0xFF)),LLIL_CONST.d(0x8)),LLIL_OR.d(LLIL_LSL.d(LLIL_AND.d(LLIL_LSR.d(LLIL_REG.d(r1),LLIL_CONST.d(0x8)),LLIL_CONST.d(0xFF)),LLIL_CONST.d(0x10)),LLIL_LSL.d(LLIL_AND.d(LLIL_REG.d(r1),LLIL_CONST.d(0xFF)),LLIL_CONST.d(0x18))))))'), + ('T', b'\x09\xba', 'LLIL_SET_REG.d(r1,LLIL_OR.d(LLIL_LSR.d(LLIL_REG.d(r1),LLIL_CONST.d(0x18)),LLIL_OR.d(LLIL_LSL.d(LLIL_AND.d(LLIL_LSR.d(LLIL_REG.d(r1),LLIL_CONST.d(0x10)),LLIL_CONST.d(0xFF)),LLIL_CONST.b(0x8)),LLIL_OR.d(LLIL_LSL.d(LLIL_AND.d(LLIL_LSR.d(LLIL_REG.d(r1),LLIL_CONST.d(0x8)),LLIL_CONST.d(0xFF)),LLIL_CONST.b(0x10)),LLIL_LSL.d(LLIL_AND.d(LLIL_REG.d(r1),LLIL_CONST.d(0xFF)),LLIL_CONST.b(0x18))))))'), ] import re |