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| author | Josh Ferrell <josh@vector35.com> | 2024-09-14 16:58:15 -0400 |
|---|---|---|
| committer | Josh Ferrell <josh@vector35.com> | 2024-09-14 16:58:15 -0400 |
| commit | 0f34db27cb60990e6b1b200820e814366ec99452 (patch) | |
| tree | 60b23a139ef94827e659f291317a97ee1700bed2 /arch/arm64/arch_arm64.cpp | |
| parent | f068de0f2d2fec6ca6d039a9648316f35e6ad965 (diff) | |
Add mpidr_el1 aarch64 sysreg
Diffstat (limited to 'arch/arm64/arch_arm64.cpp')
| -rw-r--r-- | arch/arm64/arch_arm64.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/arch_arm64.cpp b/arch/arm64/arch_arm64.cpp index ee4c2ea9..b48e6d32 100644 --- a/arch/arm64/arch_arm64.cpp +++ b/arch/arm64/arch_arm64.cpp @@ -1040,7 +1040,7 @@ class Arm64Architecture : public Architecture // on it to fill the next array. static_assert(Arm64Intrinsic::ARM64_INTRIN_AUTDA == 0, "Invalid first Arm64Intrinsic value. Please add your intrinsic further in the enum."); - + // Normal intrinsics. for (uint32_t id = Arm64Intrinsic::ARM64_INTRIN_AUTDA; id < Arm64Intrinsic::ARM64_INTRIN_NORMAL_END; id++) { result.push_back(id); @@ -1856,7 +1856,7 @@ class Arm64Architecture : public Architecture REG_TRCCIDCVR5, REG_TRCVMIDCVR5, REG_TRCCIDCVR6, REG_TRCVMIDCVR6, REG_TRCCIDCVR7, REG_TRCVMIDCVR7, REG_TRCITCTRL, REG_TRCCLAIMSET, REG_TRCCLAIMCLR, REG_TRCLAR, REG_TEECR32_EL1, REG_TEEHBR32_EL1, REG_DBGDTR_EL0, - REG_DBGDTRTX_EL0, REG_DBGVCR32_EL2, REG_SCTLR_EL1, REG_ACTLR_EL1, + REG_DBGDTRTX_EL0, REG_DBGVCR32_EL2, REG_MPIDR_EL1, REG_SCTLR_EL1, REG_ACTLR_EL1, REG_CPACR_EL1, REG_RGSR_EL1, REG_GCR_EL1, REG_TRFCR_EL1, REG_TTBR0_EL1, REG_TTBR1_EL1, REG_TCR_EL1, REG_APIAKEYLO_EL1, REG_APIAKEYHI_EL1, REG_APIBKEYLO_EL1, REG_APIBKEYHI_EL1, REG_APDAKEYLO_EL1, REG_APDAKEYHI_EL1, |