[arm64] Full review of intrinsics; lifting of many instructions added, improved, and/or fixed

Merged https://github.com/Vector35/binaryninja-api/pull/5461:
    Author: yrp <yrp604@protonmail.com>
    Date:   Sat May 25 21:00:26 2024 -0700

        arm64: lift sxtl, sxtl2, sshll, sshll2

Partial list of detailed changes squashed into this commit (see
https://github.com/Vector35/binaryninja-api/tree/arm64_improving_intrinsics
for detailed commit history):

* add lifting for sshll/sxtl

* reverted neon_intrinsics.cpp to restore scvtf intrinsics

* lifted sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and changed the lifting of uxtl/2 to be consistent with sxtl/2

* reformatted arm64test.py and added tests for sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and uxtl/2

 fix scvtf (unroll because no intrinsic) and fsub (missing register assignment) half-precision vector cases

* added preferIntrinsics setting to arm64

* added lifting for movn

* fixed incorrect int/float conversions for FMOV, made half-precision immediates survive the lift to M/HLIL

* fix missing break in SCVT; optimize MOVK

* improved preferIntrinsics

* fixed bad lifting introduced for movn

* fixed bad settings definition for preferIntrinsics

* added intrinsic definition for DUP from general register

* added direct lifting of scalar version of FADDP, and fixed intrinsics for vector version

* added direct lifting of scalar version of FABD, and fixed intrinsics for vector version

* fixes to test_gen.py: gets the correct encoding instead of sometimes getting fooled by the mnemonic

* fixed lifting of UCVTF; reviewed/fixed all intrinsics through SQXTUN

* reviewed/fixed remaining intrinsics after SQXTUN

* added lifting for FNMUL

* WIP intrinsics improvements

* WIP intrinsics improvements 2

* WIP intrinsics improvements: FCVT*_asisdmisc_R

* added B.AL, B.NV, CASP*

* direct lifting of scalar FSQRT instruction

* SETREG now elides setting of targeting zero registers

* fixed test_gen.py to correctly regenerate arm64test.py

* unroll vector MOV operations, USHL no longer uses intrinsic for scalars

* updated existing tests in arm64test.py for latest lifting changes

* fixed CASH* and CASB* incorrectly accessing temp register in comparison (resulting in comparing to NOP)

* lifting all variants of TBL as intrinsic

* fixes/improvements to test_gen.py

* lifting all variants of TBX as intrinsic

* added tests for CAS*, UMUL*, UADD*, FABD, FABS, FADDP, FMAX, FMAXNM, FMIN, FMINNM, FNEG, FNMUL, FCMEQ, FCMGE, FCMGT, FMLA, FMLS

* added tests for all aliases of SBFM

1 files changed, 18 insertions, 1 deletions

diff --git a/arch/arm64/arch_arm64.cpp b/arch/arm64/arch_arm64.cpp
index be856e79..13198af9 100644
--- a/arch/arm64/arch_arm64.cpp
+++ b/arch/arm64/arch_arm64.cpp
@@ -266,6 +266,7 @@ class Arm64Architecture : public Architecture
  protected:
 	size_t m_bits;
 	bool m_onlyDisassembleOnAlignedAddresses;
+	bool m_preferIntrinsics;
 
 	virtual bool Disassemble(const uint8_t* data, uint64_t addr, size_t maxLen, Instruction& result)
 	{
@@ -717,6 +718,7 @@ class Arm64Architecture : public Architecture
 	{
 		Ref<Settings> settings = Settings::Instance();
 		m_onlyDisassembleOnAlignedAddresses = settings->Get<bool>("arch.aarch64.disassembly.alignRequired") ? 1 : 0;
+		m_preferIntrinsics = settings->Get<bool>("arch.aarch64.disassembly.preferIntrinsics") ? 1 : 0;
 	}
 
 	bool CanAssemble() override { return true; }
@@ -1238,7 +1240,15 @@ class Arm64Architecture : public Architecture
 		}
 
 		len = 4;
-		return GetLowLevelILForInstruction(this, addr, il, instr, GetAddressSize(), m_onlyDisassembleOnAlignedAddresses);
+		return GetLowLevelILForInstruction(this, addr, il, instr, GetAddressSize(), m_onlyDisassembleOnAlignedAddresses, [&]() -> bool
+			{
+				Ref<Function> f = il.GetFunction();
+				Ref<BinaryView> v;
+				Ref<Settings> s = Settings::Instance();
+				if (s && f && (v = f->GetView()))
+					return m_preferIntrinsics && s->Get<bool>("arch.aarch64.disassembly.preferIntrinsics", v);
+				return true;
+			});
 	}
 
 
@@ -3513,6 +3523,13 @@ static void InitAarch64Settings()
 			"default" : true,
 			"description" : "Require instructions be on 4-byte aligned addresses to be disassembled."
 			})");
+	settings->RegisterSetting("arch.aarch64.disassembly.preferIntrinsics",
+			R"({
+			"title" : "AARCH64 Prefer Intrinsics for Vector Operations",
+			"type" : "boolean",
+			"default" : true,
+			"description" : "Prefer generating calls to intrinsics (where one is available) to lifting vector operations as unrolled loops (where available). Note that not all vector operations are currently lifted as either intrinsics or unrolled loops."
+			})");
 }