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| author | yrp <yrp604@protonmail.com> | 2025-08-19 23:04:48 -0700 |
|---|---|---|
| committer | Brandon Miller <bkmiller89@icloud.com> | 2025-09-18 07:20:00 -0400 |
| commit | 8b8d2dd0d39a7c19e6476810ff39a32fc099409e (patch) | |
| tree | deba2d509f2609dd31bf57754ab62fef7d88f7e4 /arch/arm64/arm64test.py | |
| parent | ece75114e87b6ad80bc21f1825ac96293272951f (diff) | |
fix ldrsw lift to sign extend in certain encodings
Diffstat (limited to 'arch/arm64/arm64test.py')
| -rwxr-xr-x | arch/arm64/arm64test.py | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm64/arm64test.py b/arch/arm64/arm64test.py index 447c45f3..90d088c9 100755 --- a/arch/arm64/arm64test.py +++ b/arch/arm64/arm64test.py @@ -12125,6 +12125,10 @@ tests_vmul = [ 'LLIL_INTRINSIC([v23],vmull_high_laneq_u32,[LLIL_REG.o(v12),LLIL_REG.o(v26),LLIL_CONST.b(0x1)])'), ] +tests_ldrsw = [ + (b'\x06\x01\x00\x98', 'LLIL_SET_REG.q(x6,LLIL_SX.q(LLIL_LOAD.d(LLIL_CONST.q(0x20))))'), +] + tests_grab_bag = [ # some vectors loads/stores that do not fill the entire register # shl v19.2d, v21.2d, #0x2 @@ -12774,6 +12778,7 @@ test_cases = \ tests_raddhn_rshrn + \ tests_ngc_sbc + \ tests_vmul + \ + tests_ldrsw + \ tests_grab_bag def il2str(il): |