[aarch64] Updating Aarch64 system registers to 2024-12 spec, fix MSR/MRS lifting to use ReadMSR/WriteMSR intrinsics that take enums, removing the sysregs from the register list of the architecture

* sysregs are no longer registers, add enum for TLBI and AT operands
* add erroneously missing cases for unsupported encodings, add enum for DC operands

1 files changed, 265 insertions, 1 deletions

diff --git a/arch/arm64/disassembler/decode.h b/arch/arm64/disassembler/decode.h
index a57d0247..4eb71bc8 100644
--- a/arch/arm64/disassembler/decode.h
+++ b/arch/arm64/disassembler/decode.h
@@ -10,7 +10,8 @@
 
 #include "encodings_dec.h"
 #include "regs.h"
-#include "sysregs.h"
+#include "sysregs_gen.h"
+#include "sysregs_fmt_gen.h"
 
 #ifdef _MSC_VER
 	#undef REG_NONE  // collides with winnt's define
@@ -113,6 +114,21 @@ enum SliceIndicator
 #define FPCR_GET_IOE(X)    SLICE(X, 8, 8)
 
 //-----------------------------------------------------------------------------
+// <tlbi_op>: TLBI operands
+//-----------------------------------------------------------------------------
+#define TLBI_OP(op1, crn, crm, op2) (((op1 & 7) << 11) | ((crn & 0xF) << 7) | ((crm & 0xF) << 3) | ((op2) & 7))
+
+//-----------------------------------------------------------------------------
+// <at_op>: AT operands
+//-----------------------------------------------------------------------------
+#define AT_OP(op1, crm, op2) (TLBI_OP(op1, 7, crm, op2))
+
+//-----------------------------------------------------------------------------
+// <dc_op>: DC operands
+//-----------------------------------------------------------------------------
+#define DC_OP(op1, crm, op2) (TLBI_OP(op1, 7, crm, op2))
+
+//-----------------------------------------------------------------------------
 // disassembly context (INPUT into disassembler)
 //-----------------------------------------------------------------------------
 
@@ -497,6 +513,251 @@ enum FlagEffect
 	FLAGEFFECT_SETS_FLOAT=3 // sets flags after float comparison
 };
 
+enum ImplSpec
+{
+	OP0 = 0,
+	OP1 = 1,
+	CRN = 2,
+	CRM = 3,
+	OP2 = 4
+};
+
+enum ATOp
+{
+	AT_OP_INVALID=-1,
+	AT_OP_S1E1R=AT_OP(0b000, 0b1000, 0b000),
+	AT_OP_S1E1W=AT_OP(0b000, 0b1000, 0b001),
+	AT_OP_S1E0R=AT_OP(0b000, 0b1000, 0b010),
+	AT_OP_S1E0W=AT_OP(0b000, 0b1000, 0b011),
+	AT_OP_S1E1RP=AT_OP(0b000, 0b1001, 0b000),
+	AT_OP_S1E1WP=AT_OP(0b000, 0b1001, 0b001),
+	AT_OP_S1E1A=AT_OP(0b000, 0b1001, 0b010),
+	AT_OP_S1E2R=AT_OP(0b100, 0b1000, 0b000),
+	AT_OP_S1E2W=AT_OP(0b100, 0b1000, 0b001),
+	AT_OP_S12E1R=AT_OP(0b100, 0b1000, 0b100),
+	AT_OP_S12E1W=AT_OP(0b100, 0b1000, 0b101),
+	AT_OP_S12E0R=AT_OP(0b100, 0b1000, 0b110),
+	AT_OP_S12E0W=AT_OP(0b100, 0b1000, 0b111),
+	AT_OP_S1E2A=AT_OP(0b100, 0b1001, 0b010),
+	AT_OP_S1E3R=AT_OP(0b110, 0b1000, 0b000),
+	AT_OP_S1E3W=AT_OP(0b110, 0b1000, 0b001),
+	AT_OP_S1E3A=AT_OP(0b110, 0b1001, 0b010),
+};
+
+enum TlbiOp
+{
+	TLBI_INVALID=-1,
+	TLBI_VMALLE1OS=TLBI_OP(0b000, 0b1000, 0b0001, 0b000),
+	TLBI_VAE1OS=TLBI_OP(0b000, 0b1000, 0b0001, 0b001),
+	TLBI_ASIDE1OS=TLBI_OP(0b000, 0b1000, 0b0001, 0b010),
+	TLBI_VAAE1OS=TLBI_OP(0b000, 0b1000, 0b0001, 0b011),
+	TLBI_VALE1OS=TLBI_OP(0b000, 0b1000, 0b0001, 0b101),
+	TLBI_VAALE1OS=TLBI_OP(0b000, 0b1000, 0b0001, 0b111),
+	TLBI_RVAE1IS=TLBI_OP(0b000, 0b1000, 0b0010, 0b001),
+	TLBI_RVAAE1IS=TLBI_OP(0b000, 0b1000, 0b0010, 0b011),
+	TLBI_RVALE1IS=TLBI_OP(0b000, 0b1000, 0b0010, 0b101),
+	TLBI_RVAALE1IS=TLBI_OP(0b000, 0b1000, 0b0010, 0b111),
+	TLBI_VMALLE1IS=TLBI_OP(0b000, 0b1000, 0b0011, 0b000),
+	TLBI_VAE1IS=TLBI_OP(0b000, 0b1000, 0b0011, 0b001),
+	TLBI_ASIDE1IS=TLBI_OP(0b000, 0b1000, 0b0011, 0b010),
+	TLBI_VAAE1IS=TLBI_OP(0b000, 0b1000, 0b0011, 0b011),
+	TLBI_VALE1IS=TLBI_OP(0b000, 0b1000, 0b0011, 0b101),
+	TLBI_VAALE1IS=TLBI_OP(0b000, 0b1000, 0b0011, 0b111),
+	TLBI_RVAE1OS=TLBI_OP(0b000, 0b1000, 0b0101, 0b001),
+	TLBI_RVAAE1OS=TLBI_OP(0b000, 0b1000, 0b0101, 0b011),
+	TLBI_RVALE1OS=TLBI_OP(0b000, 0b1000, 0b0101, 0b101),
+	TLBI_RVAALE1OS=TLBI_OP(0b000, 0b1000, 0b0101, 0b111),
+	TLBI_RVAE1=TLBI_OP(0b000, 0b1000, 0b0110, 0b001),
+	TLBI_RVAAE1=TLBI_OP(0b000, 0b1000, 0b0110, 0b011),
+	TLBI_RVALE1=TLBI_OP(0b000, 0b1000, 0b0110, 0b101),
+	TLBI_RVAALE1=TLBI_OP(0b000, 0b1000, 0b0110, 0b111),
+	TLBI_VMALLE1=TLBI_OP(0b000, 0b1000, 0b0111, 0b000),
+	TLBI_VAE1=TLBI_OP(0b000, 0b1000, 0b0111, 0b001),
+	TLBI_ASIDE1=TLBI_OP(0b000, 0b1000, 0b0111, 0b010),
+	TLBI_VAAE1=TLBI_OP(0b000, 0b1000, 0b0111, 0b011),
+	TLBI_VALE1=TLBI_OP(0b000, 0b1000, 0b0111, 0b101),
+	TLBI_VAALE1=TLBI_OP(0b000, 0b1000, 0b0111, 0b111),
+	TLBI_VMALLE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0001, 0b000),
+	TLBI_VAE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0001, 0b001),
+	TLBI_ASIDE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0001, 0b010),
+	TLBI_VAAE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0001, 0b011),
+	TLBI_VALE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0001, 0b101),
+	TLBI_VAALE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0001, 0b111),
+	TLBI_RVAE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0010, 0b001),
+	TLBI_RVAAE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0010, 0b011),
+	TLBI_RVALE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0010, 0b101),
+	TLBI_RVAALE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0010, 0b111),
+	TLBI_VMALLE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0011, 0b000),
+	TLBI_VAE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0011, 0b001),
+	TLBI_ASIDE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0011, 0b010),
+	TLBI_VAAE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0011, 0b011),
+	TLBI_VALE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0011, 0b101),
+	TLBI_VAALE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0011, 0b111),
+	TLBI_RVAE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0101, 0b001),
+	TLBI_RVAAE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0101, 0b011),
+	TLBI_RVALE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0101, 0b101),
+	TLBI_RVAALE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0101, 0b111),
+	TLBI_RVAE1NXS=TLBI_OP(0b000, 0b1001, 0b0110, 0b001),
+	TLBI_RVAAE1NXS=TLBI_OP(0b000, 0b1001, 0b0110, 0b011),
+	TLBI_RVALE1NXS=TLBI_OP(0b000, 0b1001, 0b0110, 0b101),
+	TLBI_RVAALE1NXS=TLBI_OP(0b000, 0b1001, 0b0110, 0b111),
+	TLBI_VMALLE1NXS=TLBI_OP(0b000, 0b1001, 0b0111, 0b000),
+	TLBI_VAE1NXS=TLBI_OP(0b000, 0b1001, 0b0111, 0b001),
+	TLBI_ASIDE1NXS=TLBI_OP(0b000, 0b1001, 0b0111, 0b010),
+	TLBI_VAAE1NXS=TLBI_OP(0b000, 0b1001, 0b0111, 0b011),
+	TLBI_VALE1NXS=TLBI_OP(0b000, 0b1001, 0b0111, 0b101),
+	TLBI_VAALE1NXS=TLBI_OP(0b000, 0b1001, 0b0111, 0b111),
+	TLBI_IPAS2E1IS=TLBI_OP(0b100, 0b1000, 0b0000, 0b001),
+	TLBI_RIPAS2E1IS=TLBI_OP(0b100, 0b1000, 0b0000, 0b010),
+	TLBI_IPAS2LE1IS=TLBI_OP(0b100, 0b1000, 0b0000, 0b101),
+	TLBI_RIPAS2LE1IS=TLBI_OP(0b100, 0b1000, 0b0000, 0b110),
+	TLBI_ALLE2OS=TLBI_OP(0b100, 0b1000, 0b0001, 0b000),
+	TLBI_VAE2OS=TLBI_OP(0b100, 0b1000, 0b0001, 0b001),
+	TLBI_ALLE1OS=TLBI_OP(0b100, 0b1000, 0b0001, 0b100),
+	TLBI_VALE2OS=TLBI_OP(0b100, 0b1000, 0b0001, 0b101),
+	TLBI_VMALLS12E1OS=TLBI_OP(0b100, 0b1000, 0b0001, 0b110),
+	TLBI_RVAE2IS=TLBI_OP(0b100, 0b1000, 0b0010, 0b001),
+	TLBI_VMALLWS2E1IS=TLBI_OP(0b100, 0b1000, 0b0010, 0b010),
+	TLBI_RVALE2IS=TLBI_OP(0b100, 0b1000, 0b0010, 0b101),
+	TLBI_ALLE2IS=TLBI_OP(0b100, 0b1000, 0b0011, 0b000),
+	TLBI_VAE2IS=TLBI_OP(0b100, 0b1000, 0b0011, 0b001),
+	TLBI_ALLE1IS=TLBI_OP(0b100, 0b1000, 0b0011, 0b100),
+	TLBI_VALE2IS=TLBI_OP(0b100, 0b1000, 0b0011, 0b101),
+	TLBI_VMALLS12E1IS=TLBI_OP(0b100, 0b1000, 0b0011, 0b110),
+	TLBI_IPAS2E1OS=TLBI_OP(0b100, 0b1000, 0b0100, 0b000),
+	TLBI_IPAS2E1=TLBI_OP(0b100, 0b1000, 0b0100, 0b001),
+	TLBI_RIPAS2E1=TLBI_OP(0b100, 0b1000, 0b0100, 0b010),
+	TLBI_RIPAS2E1OS=TLBI_OP(0b100, 0b1000, 0b0100, 0b011),
+	TLBI_IPAS2LE1OS=TLBI_OP(0b100, 0b1000, 0b0100, 0b100),
+	TLBI_IPAS2LE1=TLBI_OP(0b100, 0b1000, 0b0100, 0b101),
+	TLBI_RIPAS2LE1=TLBI_OP(0b100, 0b1000, 0b0100, 0b110),
+	TLBI_RIPAS2LE1OS=TLBI_OP(0b100, 0b1000, 0b0100, 0b111),
+	TLBI_RVAE2OS=TLBI_OP(0b100, 0b1000, 0b0101, 0b001),
+	TLBI_VMALLWS2E1OS=TLBI_OP(0b100, 0b1000, 0b0101, 0b010),
+	TLBI_RVALE2OS=TLBI_OP(0b100, 0b1000, 0b0101, 0b101),
+	TLBI_RVAE2=TLBI_OP(0b100, 0b1000, 0b0110, 0b001),
+	TLBI_VMALLWS2E1=TLBI_OP(0b100, 0b1000, 0b0110, 0b010),
+	TLBI_RVALE2=TLBI_OP(0b100, 0b1000, 0b0110, 0b101),
+	TLBI_ALLE2=TLBI_OP(0b100, 0b1000, 0b0111, 0b000),
+	TLBI_VAE2=TLBI_OP(0b100, 0b1000, 0b0111, 0b001),
+	TLBI_ALLE1=TLBI_OP(0b100, 0b1000, 0b0111, 0b100),
+	TLBI_VALE2=TLBI_OP(0b100, 0b1000, 0b0111, 0b101),
+	TLBI_VMALLS12E1=TLBI_OP(0b100, 0b1000, 0b0111, 0b110),
+	TLBI_IPAS2E1ISNXS=TLBI_OP(0b100, 0b1001, 0b0000, 0b001),
+	TLBI_RIPAS2E1ISNXS=TLBI_OP(0b100, 0b1001, 0b0000, 0b010),
+	TLBI_IPAS2LE1ISNXS=TLBI_OP(0b100, 0b1001, 0b0000, 0b101),
+	TLBI_RIPAS2LE1ISNXS=TLBI_OP(0b100, 0b1001, 0b0000, 0b110),
+	TLBI_ALLE2OSNXS=TLBI_OP(0b100, 0b1001, 0b0001, 0b000),
+	TLBI_VAE2OSNXS=TLBI_OP(0b100, 0b1001, 0b0001, 0b001),
+	TLBI_ALLE1OSNXS=TLBI_OP(0b100, 0b1001, 0b0001, 0b100),
+	TLBI_VALE2OSNXS=TLBI_OP(0b100, 0b1001, 0b0001, 0b101),
+	TLBI_VMALLS12E1OSNXS=TLBI_OP(0b100, 0b1001, 0b0001, 0b110),
+	TLBI_RVAE2ISNXS=TLBI_OP(0b100, 0b1001, 0b0010, 0b001),
+	TLBI_VMALLWS2E1ISNXS=TLBI_OP(0b100, 0b1001, 0b0010, 0b010),
+	TLBI_RVALE2ISNXS=TLBI_OP(0b100, 0b1001, 0b0010, 0b101),
+	TLBI_ALLE2ISNXS=TLBI_OP(0b100, 0b1001, 0b0011, 0b000),
+	TLBI_VAE2ISNXS=TLBI_OP(0b100, 0b1001, 0b0011, 0b001),
+	TLBI_ALLE1ISNXS=TLBI_OP(0b100, 0b1001, 0b0011, 0b100),
+	TLBI_VALE2ISNXS=TLBI_OP(0b100, 0b1001, 0b0011, 0b101),
+	TLBI_VMALLS12E1ISNXS=TLBI_OP(0b100, 0b1001, 0b0011, 0b110),
+	TLBI_IPAS2E1OSNXS=TLBI_OP(0b100, 0b1001, 0b0100, 0b000),
+	TLBI_IPAS2E1NXS=TLBI_OP(0b100, 0b1001, 0b0100, 0b001),
+	TLBI_RIPAS2E1NXS=TLBI_OP(0b100, 0b1001, 0b0100, 0b010),
+	TLBI_RIPAS2E1OSNXS=TLBI_OP(0b100, 0b1001, 0b0100, 0b011),
+	TLBI_IPAS2LE1OSNXS=TLBI_OP(0b100, 0b1001, 0b0100, 0b100),
+	TLBI_IPAS2LE1NXS=TLBI_OP(0b100, 0b1001, 0b0100, 0b101),
+	TLBI_RIPAS2LE1NXS=TLBI_OP(0b100, 0b1001, 0b0100, 0b110),
+	TLBI_RIPAS2LE1OSNXS=TLBI_OP(0b100, 0b1001, 0b0100, 0b111),
+	TLBI_RVAE2OSNXS=TLBI_OP(0b100, 0b1001, 0b0101, 0b001),
+	TLBI_VMALLWS2E1OSNXS=TLBI_OP(0b100, 0b1001, 0b0101, 0b010),
+	TLBI_RVALE2OSNXS=TLBI_OP(0b100, 0b1001, 0b0101, 0b101),
+	TLBI_RVAE2NXS=TLBI_OP(0b100, 0b1001, 0b0110, 0b001),
+	TLBI_VMALLWS2E1NXS=TLBI_OP(0b100, 0b1001, 0b0110, 0b010),
+	TLBI_RVALE2NXS=TLBI_OP(0b100, 0b1001, 0b0110, 0b101),
+	TLBI_ALLE2NXS=TLBI_OP(0b100, 0b1001, 0b0111, 0b000),
+	TLBI_VAE2NXS=TLBI_OP(0b100, 0b1001, 0b0111, 0b001),
+	TLBI_ALLE1NXS=TLBI_OP(0b100, 0b1001, 0b0111, 0b100),
+	TLBI_VALE2NXS=TLBI_OP(0b100, 0b1001, 0b0111, 0b101),
+	TLBI_VMALLS12E1NXS=TLBI_OP(0b100, 0b1001, 0b0111, 0b110),
+	TLBI_ALLE3OS=TLBI_OP(0b110, 0b1000, 0b0001, 0b000),
+	TLBI_VAE3OS=TLBI_OP(0b110, 0b1000, 0b0001, 0b001),
+	TLBI_PAALLOS=TLBI_OP(0b110, 0b1000, 0b0001, 0b100),
+	TLBI_VALE3OS=TLBI_OP(0b110, 0b1000, 0b0001, 0b101),
+	TLBI_RVAE3IS=TLBI_OP(0b110, 0b1000, 0b0010, 0b001),
+	TLBI_RVALE3IS=TLBI_OP(0b110, 0b1000, 0b0010, 0b101),
+	TLBI_ALLE3IS=TLBI_OP(0b110, 0b1000, 0b0011, 0b000),
+	TLBI_VAE3IS=TLBI_OP(0b110, 0b1000, 0b0011, 0b001),
+	TLBI_VALE3IS=TLBI_OP(0b110, 0b1000, 0b0011, 0b101),
+	TLBI_RPAOS=TLBI_OP(0b110, 0b1000, 0b0100, 0b011),
+	TLBI_RPALOS=TLBI_OP(0b110, 0b1000, 0b0100, 0b111),
+	TLBI_RVAE3OS=TLBI_OP(0b110, 0b1000, 0b0101, 0b001),
+	TLBI_RVALE3OS=TLBI_OP(0b110, 0b1000, 0b0101, 0b101),
+	TLBI_RVAE3=TLBI_OP(0b110, 0b1000, 0b0110, 0b001),
+	TLBI_RVALE3=TLBI_OP(0b110, 0b1000, 0b0110, 0b101),
+	TLBI_ALLE3=TLBI_OP(0b110, 0b1000, 0b0111, 0b000),
+	TLBI_VAE3=TLBI_OP(0b110, 0b1000, 0b0111, 0b001),
+	TLBI_PAALL=TLBI_OP(0b110, 0b1000, 0b0111, 0b100),
+	TLBI_VALE3=TLBI_OP(0b110, 0b1000, 0b0111, 0b101),
+	TLBI_ALLE3OSNXS=TLBI_OP(0b110, 0b1001, 0b0001, 0b000),
+	TLBI_VAE3OSNXS=TLBI_OP(0b110, 0b1001, 0b0001, 0b001),
+	TLBI_VALE3OSNXS=TLBI_OP(0b110, 0b1001, 0b0001, 0b101),
+	TLBI_RVAE3ISNXS=TLBI_OP(0b110, 0b1001, 0b0010, 0b001),
+	TLBI_RVALE3ISNXS=TLBI_OP(0b110, 0b1001, 0b0010, 0b101),
+	TLBI_ALLE3ISNXS=TLBI_OP(0b110, 0b1001, 0b0011, 0b000),
+	TLBI_VAE3ISNXS=TLBI_OP(0b110, 0b1001, 0b0011, 0b001),
+	TLBI_VALE3ISNXS=TLBI_OP(0b110, 0b1001, 0b0011, 0b101),
+	TLBI_RVAE3OSNXS=TLBI_OP(0b110, 0b1001, 0b0101, 0b001),
+	TLBI_RVALE3OSNXS=TLBI_OP(0b110, 0b1001, 0b0101, 0b101),
+	TLBI_RVAE3NXS=TLBI_OP(0b110, 0b1001, 0b0110, 0b001),
+	TLBI_RVALE3NXS=TLBI_OP(0b110, 0b1001, 0b0110, 0b101),
+	TLBI_ALLE3NXS=TLBI_OP(0b110, 0b1001, 0b0111, 0b000),
+	TLBI_VAE3NXS=TLBI_OP(0b110, 0b1001, 0b0111, 0b001),
+	TLBI_VALE3NXS=TLBI_OP(0b110, 0b1001, 0b0111, 0b101),
+};
+
+enum DCOp
+{
+	DC_OP_INVALID=-1,
+	DC_OP_IVAC=DC_OP(0b000, 0b0110, 0b001),
+	DC_OP_ISW=DC_OP(0b000, 0b0110, 0b010),
+	DC_OP_IGVAC=DC_OP(0b000, 0b0110, 0b011),
+	DC_OP_IGSW=DC_OP(0b000, 0b0110, 0b100),
+	DC_OP_IGDVAC=DC_OP(0b000, 0b0110, 0b101),
+	DC_OP_IGDSW=DC_OP(0b000, 0b0110, 0b110),
+	DC_OP_CSW=DC_OP(0b000, 0b1010, 0b010),
+	DC_OP_CGSW=DC_OP(0b000, 0b1010, 0b100),
+	DC_OP_CGDSW=DC_OP(0b000, 0b1010, 0b110),
+	DC_OP_CISW=DC_OP(0b000, 0b1110, 0b010),
+	DC_OP_CIGSW=DC_OP(0b000, 0b1110, 0b100),
+	DC_OP_CIGDSW=DC_OP(0b000, 0b1110, 0b110),
+	DC_OP_CIVAPS=DC_OP(0b000, 0b1111, 0b001),
+	DC_OP_CIGDVAPS=DC_OP(0b000, 0b1111, 0b101),
+	DC_OP_ZVA=DC_OP(0b011, 0b0100, 0b001),
+	DC_OP_GVA=DC_OP(0b011, 0b0100, 0b011),
+	DC_OP_GZVA=DC_OP(0b011, 0b0100, 0b100),
+	DC_OP_CVAC=DC_OP(0b011, 0b1010, 0b001),
+	DC_OP_CGVAC=DC_OP(0b011, 0b1010, 0b011),
+	DC_OP_CGDVAC=DC_OP(0b011, 0b1010, 0b101),
+	DC_OP_CVAOC=DC_OP(0b011, 0b1011, 0b000),
+	DC_OP_CVAU=DC_OP(0b011, 0b1011, 0b001),
+	DC_OP_CGDVAOC=DC_OP(0b011, 0b1011, 0b111),
+	DC_OP_CVAP=DC_OP(0b011, 0b1100, 0b001),
+	DC_OP_CGVAP=DC_OP(0b011, 0b1100, 0b011),
+	DC_OP_CGDVAP=DC_OP(0b011, 0b1100, 0b101),
+	DC_OP_CVADP=DC_OP(0b011, 0b1101, 0b001),
+	DC_OP_CGVADP=DC_OP(0b011, 0b1101, 0b011),
+	DC_OP_CGDVADP=DC_OP(0b011, 0b1101, 0b101),
+	DC_OP_CIVAC=DC_OP(0b011, 0b1110, 0b001),
+	DC_OP_CIGVAC=DC_OP(0b011, 0b1110, 0b011),
+	DC_OP_CIGDVAC=DC_OP(0b011, 0b1110, 0b101),
+	DC_OP_CIVAOC=DC_OP(0b011, 0b1111, 0b000),
+	DC_OP_CIGDVAOC=DC_OP(0b011, 0b1111, 0b111),
+	DC_OP_CIPAE=DC_OP(0b100, 0b1110, 0b000),
+	DC_OP_CIGDPAE=DC_OP(0b100, 0b1110, 0b111),
+	DC_OP_CIPAPA=DC_OP(0b110, 0b1110, 0b001),
+	DC_OP_CIGDPAPA=DC_OP(0b110, 0b1110, 0b101),
+};
+
 #ifndef __cplusplus
 typedef enum SystemReg SystemReg;
 typedef enum OperandClass OperandClass;
@@ -507,6 +768,8 @@ typedef enum Operation Operation;
 typedef enum Group Group;
 typedef enum ArrangementSpec ArrangementSpec;
 typedef enum SliceIndicator SliceIndicator;
+typedef enum ImplSpec ImplSpec;
+typedef enum TlbiOp TlbiOp;
 #endif
 
 #define MAX_REGISTERS 5
@@ -574,6 +837,7 @@ extern "C"
 
 	int aarch64_decompose(uint32_t instructionValue, Instruction* instr, uint64_t address);
 	size_t get_register_size(enum Register);
+	// const char* tlbi_op(int32_t op);
 
 #ifdef __cplusplus
 }