diff options
| author | Galen Williamson <galen@vector35.com> | 2025-03-25 21:27:51 -0400 |
|---|---|---|
| committer | Galen Williamson <galen@vector35.com> | 2025-03-31 18:31:33 -0400 |
| commit | b095215397ca8fe7e9808f312403ec4494de76f6 (patch) | |
| tree | 5eebe61a44d2f95aa5fadd78d9974234fca376be /arch/arm64/disassembler/decode2.c | |
| parent | 8093106217331012734564301118244748535715 (diff) | |
[aarch64] Updating Aarch64 system registers to 2024-12 spec, fix MSR/MRS lifting to use ReadMSR/WriteMSR intrinsics that take enums, removing the sysregs from the register list of the architecture
* sysregs are no longer registers, add enum for TLBI and AT operands
* add erroneously missing cases for unsupported encodings, add enum for DC operands
Diffstat (limited to 'arch/arm64/disassembler/decode2.c')
| -rw-r--r-- | arch/arm64/disassembler/decode2.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm64/disassembler/decode2.c b/arch/arm64/disassembler/decode2.c index 0d0d7c14..7dbe3699 100644 --- a/arch/arm64/disassembler/decode2.c +++ b/arch/arm64/disassembler/decode2.c @@ -27518,7 +27518,8 @@ int SYS(context *ctx, Instruction *instr) if(ctx->CRn==7 && SysOp(ctx->op1,7,ctx->CRm,ctx->op2)==Sys_DC) return DC_SYS(ctx, instr); if(ctx->op1==3 && ctx->CRn==7 && ctx->CRm==3 && ctx->op2==5) return DVP_SYS(ctx, instr); if(ctx->CRn==7 && SysOp(ctx->op1,7,ctx->CRm,ctx->op2)==Sys_IC) return IC_SYS(ctx, instr); - if(ctx->CRn==8 && SysOp(ctx->op1,8,ctx->CRm,ctx->op2)==Sys_TLBI) return TLBI_SYS(ctx, instr); + // if(ctx->CRn==8 && SysOp(ctx->op1,8,ctx->CRm,ctx->op2)==Sys_TLBI) return TLBI_SYS(ctx, instr); + if(((ctx->CRn&14)==8) && SysOp(ctx->op1,ctx->CRn,ctx->CRm,ctx->op2)==Sys_TLBI) return TLBI_SYS(ctx, instr); OK(ENC_SYS_CR_SYSTEMINSTRS); } return rc; @@ -27666,8 +27667,10 @@ int TLBI_SYS(context *ctx, Instruction *instr) { int rc = DECODE_STATUS_UNMATCHED; /* class iclass_system */ - /* 1101010100|L=0|op0=01|op1=xxx|CRn=1000|CRm=xxxx|op2=xxx|Rt=xxxxx */ - if((INSWORD & 0xFFF8F000)==0xD5088000) { + // /* 1101010100|L=0|op0=01|op1=xxx|CRn=1000|CRm=xxxx|op2=xxx|Rt=xxxxx */ + // if((INSWORD & 0xFFF8F000)==0xD5088000) { + /* 110|101|0100|L=0|01|op1=xxx|CRn=100x|CRm=xxxx|op2=xxx|Rt=xxxxx */ + if((INSWORD & 0xFFF8E000)==0xD5088000) { decode_fields32(ENC_TLBI_SYS_CR_SYSTEMINSTRS, ctx, instr); OK(ENC_TLBI_SYS_CR_SYSTEMINSTRS); } |