diff options
| author | Galen Williamson <galen@vector35.com> | 2025-03-25 21:27:51 -0400 |
|---|---|---|
| committer | Galen Williamson <galen@vector35.com> | 2025-03-31 18:31:33 -0400 |
| commit | b095215397ca8fe7e9808f312403ec4494de76f6 (patch) | |
| tree | 5eebe61a44d2f95aa5fadd78d9974234fca376be /arch/arm64/disassembler/decode_fields32.c | |
| parent | 8093106217331012734564301118244748535715 (diff) | |
[aarch64] Updating Aarch64 system registers to 2024-12 spec, fix MSR/MRS lifting to use ReadMSR/WriteMSR intrinsics that take enums, removing the sysregs from the register list of the architecture
* sysregs are no longer registers, add enum for TLBI and AT operands
* add erroneously missing cases for unsupported encodings, add enum for DC operands
Diffstat (limited to 'arch/arm64/disassembler/decode_fields32.c')
| -rw-r--r-- | arch/arm64/disassembler/decode_fields32.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/disassembler/decode_fields32.c b/arch/arm64/disassembler/decode_fields32.c index 63e479cd..b5e26540 100644 --- a/arch/arm64/disassembler/decode_fields32.c +++ b/arch/arm64/disassembler/decode_fields32.c @@ -1626,6 +1626,7 @@ void decode_fields32(enum ENCODING enc, context *ctx, Instruction *instr) case ENC_XAFLAG_M_PSTATE: case ENC_XPACLRI_HI_HINTS: case ENC_YIELD_HI_HINTS: + //['19:1101010100000:1101010100000', '16:op1:011', '12:0100:0100', '8:CRm:0111', '5:op2:110', '0:Rt:11111'] // xxxxxxxxxx|L=x|op0=xx|op1=xxx|CRn=xxxx|CRm=xxxx|op2=xxx|Rt=xxxxx ctx->L = (insword>>21)&1; ctx->op0 = (insword>>19)&3; |