diff options
| author | Rusty Wagner <rusty.wagner@gmail.com> | 2024-03-05 19:50:13 -0500 |
|---|---|---|
| committer | Rusty Wagner <rusty.wagner@gmail.com> | 2024-03-05 20:34:34 -0500 |
| commit | e093c21ed880ac3eb72119be15093ee04f8ce299 (patch) | |
| tree | 9f720ebdc0ae415734b1199ed341668c69710a94 /arch/arm64/disassembler/encodings_dec.c | |
| parent | 0609276712622908254065546102381466033141 (diff) | |
Move architecture modules into the API repo
Diffstat (limited to 'arch/arm64/disassembler/encodings_dec.c')
| -rw-r--r-- | arch/arm64/disassembler/encodings_dec.c | 4286 |
1 files changed, 4286 insertions, 0 deletions
diff --git a/arch/arm64/disassembler/encodings_dec.c b/arch/arm64/disassembler/encodings_dec.c new file mode 100644 index 00000000..e96b9a66 --- /dev/null +++ b/arch/arm64/disassembler/encodings_dec.c @@ -0,0 +1,4286 @@ +/* GENERATED FILE */ +/* this is the "decoding" side of encodings, no string mappings */ + +#include "operations.h" +#include "encodings_dec.h" + +enum Operation enc_to_oper(enum ENCODING enc) +{ + switch(enc) { + case ENC_ABS_ASISDMISC_R: + case ENC_ABS_ASIMDMISC_R: + case ENC_ABS_Z_P_Z_: + return ARM64_ABS; + case ENC_ADC_32_ADDSUB_CARRY: + case ENC_ADC_64_ADDSUB_CARRY: + return ARM64_ADC; + case ENC_ADCLB_Z_ZZZ_: + return ARM64_ADCLB; + case ENC_ADCLT_Z_ZZZ_: + return ARM64_ADCLT; + case ENC_ADCS_32_ADDSUB_CARRY: + case ENC_ADCS_64_ADDSUB_CARRY: + return ARM64_ADCS; + case ENC_ADD_32_ADDSUB_EXT: + case ENC_ADD_64_ADDSUB_EXT: + case ENC_ADD_32_ADDSUB_IMM: + case ENC_ADD_64_ADDSUB_IMM: + case ENC_ADD_32_ADDSUB_SHIFT: + case ENC_ADD_64_ADDSUB_SHIFT: + case ENC_ADD_ASISDSAME_ONLY: + case ENC_ADD_ASIMDSAME_ONLY: + case ENC_ADD_Z_P_ZZ_: + case ENC_ADD_Z_ZI_: + case ENC_ADD_Z_ZZ_: + return ARM64_ADD; + case ENC_ADDG_64_ADDSUB_IMMTAGS: + return ARM64_ADDG; + case ENC_ADDHA_ZA_PP_Z_32: + case ENC_ADDHA_ZA_PP_Z_64: + return ARM64_ADDHA; + case ENC_ADDHN_ASIMDDIFF_N: + return ARM64_ADDHN; + //case ENC_ADDHN_ASIMDDIFF_N: + // return ARM64_ADDHN2; + case ENC_ADDHNB_Z_ZZ_: + return ARM64_ADDHNB; + case ENC_ADDHNT_Z_ZZ_: + return ARM64_ADDHNT; + case ENC_ADDP_ASISDPAIR_ONLY: + case ENC_ADDP_ASIMDSAME_ONLY: + case ENC_ADDP_Z_P_ZZ_: + return ARM64_ADDP; + case ENC_ADDPL_R_RI_: + return ARM64_ADDPL; + case ENC_ADDS_32S_ADDSUB_EXT: + case ENC_ADDS_64S_ADDSUB_EXT: + case ENC_ADDS_32S_ADDSUB_IMM: + case ENC_ADDS_64S_ADDSUB_IMM: + case ENC_ADDS_32_ADDSUB_SHIFT: + case ENC_ADDS_64_ADDSUB_SHIFT: + return ARM64_ADDS; + case ENC_ADDV_ASIMDALL_ONLY: + return ARM64_ADDV; + case ENC_ADDVA_ZA_PP_Z_32: + case ENC_ADDVA_ZA_PP_Z_64: + return ARM64_ADDVA; + case ENC_ADDVL_R_RI_: + return ARM64_ADDVL; + case ENC_ADR_ONLY_PCRELADDR: + case ENC_ADR_Z_AZ_SD_SAME_SCALED: + case ENC_ADR_Z_AZ_D_S32_SCALED: + case ENC_ADR_Z_AZ_D_U32_SCALED: + return ARM64_ADR; + case ENC_ADRP_ONLY_PCRELADDR: + return ARM64_ADRP; + case ENC_AESD_B_CRYPTOAES: + case ENC_AESD_Z_ZZ_: + return ARM64_AESD; + case ENC_AESE_B_CRYPTOAES: + case ENC_AESE_Z_ZZ_: + return ARM64_AESE; + case ENC_AESIMC_B_CRYPTOAES: + case ENC_AESIMC_Z_Z_: + return ARM64_AESIMC; + case ENC_AESMC_B_CRYPTOAES: + case ENC_AESMC_Z_Z_: + return ARM64_AESMC; + case ENC_AND_ASIMDSAME_ONLY: + case ENC_AND_32_LOG_IMM: + case ENC_AND_64_LOG_IMM: + case ENC_AND_32_LOG_SHIFT: + case ENC_AND_64_LOG_SHIFT: + case ENC_AND_P_P_PP_Z: + case ENC_AND_Z_P_ZZ_: + case ENC_AND_Z_ZI_: + case ENC_AND_Z_ZZ_: + return ARM64_AND; + case ENC_ANDS_32S_LOG_IMM: + case ENC_ANDS_64S_LOG_IMM: + case ENC_ANDS_32_LOG_SHIFT: + case ENC_ANDS_64_LOG_SHIFT: + case ENC_ANDS_P_P_PP_Z: + return ARM64_ANDS; + case ENC_ANDV_R_P_Z_: + return ARM64_ANDV; + case ENC_ASR_ASRV_32_DP_2SRC: + case ENC_ASR_ASRV_64_DP_2SRC: + case ENC_ASR_SBFM_32M_BITFIELD: + case ENC_ASR_SBFM_64M_BITFIELD: + case ENC_ASR_Z_P_ZI_: + case ENC_ASR_Z_P_ZW_: + case ENC_ASR_Z_P_ZZ_: + case ENC_ASR_Z_ZI_: + case ENC_ASR_Z_ZW_: + return ARM64_ASR; + case ENC_ASRD_Z_P_ZI_: + return ARM64_ASRD; + case ENC_ASRR_Z_P_ZZ_: + return ARM64_ASRR; + case ENC_ASRV_32_DP_2SRC: + case ENC_ASRV_64_DP_2SRC: + return ARM64_ASRV; + case ENC_AT_SYS_CR_SYSTEMINSTRS: + return ARM64_AT; + case ENC_AUTDA_64P_DP_1SRC: + return ARM64_AUTDA; + case ENC_AUTDB_64P_DP_1SRC: + return ARM64_AUTDB; + case ENC_AUTDZA_64Z_DP_1SRC: + return ARM64_AUTDZA; + case ENC_AUTDZB_64Z_DP_1SRC: + return ARM64_AUTDZB; + case ENC_AUTIA_64P_DP_1SRC: + return ARM64_AUTIA; + case ENC_AUTIA1716_HI_HINTS: + return ARM64_AUTIA1716; + case ENC_AUTIASP_HI_HINTS: + return ARM64_AUTIASP; + case ENC_AUTIAZ_HI_HINTS: + return ARM64_AUTIAZ; + case ENC_AUTIB_64P_DP_1SRC: + return ARM64_AUTIB; + case ENC_AUTIB1716_HI_HINTS: + return ARM64_AUTIB1716; + case ENC_AUTIBSP_HI_HINTS: + return ARM64_AUTIBSP; + case ENC_AUTIBZ_HI_HINTS: + return ARM64_AUTIBZ; + case ENC_AUTIZA_64Z_DP_1SRC: + return ARM64_AUTIZA; + case ENC_AUTIZB_64Z_DP_1SRC: + return ARM64_AUTIZB; + case ENC_AXFLAG_M_PSTATE: + return ARM64_AXFLAG; + case ENC_B_ONLY_CONDBRANCH: + case ENC_B_ONLY_BRANCH_IMM: + return ARM64_B; + case ENC_BCAX_VVV16_CRYPTO4: + case ENC_BCAX_Z_ZZZ_: + return ARM64_BCAX; + case ENC_BDEP_Z_ZZ_: + return ARM64_BDEP; + case ENC_BEXT_Z_ZZ_: + return ARM64_BEXT; + case ENC_BFC_BFM_32M_BITFIELD: + case ENC_BFC_BFM_64M_BITFIELD: + return ARM64_BFC; + case ENC_BFCVT_BS_FLOATDP1: + case ENC_BFCVT_Z_P_Z_S2BF: + return ARM64_BFCVT; + case ENC_BFCVTN_ASIMDMISC_4S: + return ARM64_BFCVTN; + //case ENC_BFCVTN_ASIMDMISC_4S: + // return ARM64_BFCVTN2; + case ENC_BFCVTNT_Z_P_Z_S2BF: + return ARM64_BFCVTNT; + case ENC_BFDOT_ASIMDELEM_E: + case ENC_BFDOT_ASIMDSAME2_D: + case ENC_BFDOT_Z_ZZZ_: + case ENC_BFDOT_Z_ZZZI_: + return ARM64_BFDOT; + case ENC_BFI_BFM_32M_BITFIELD: + case ENC_BFI_BFM_64M_BITFIELD: + return ARM64_BFI; + case ENC_BFM_32M_BITFIELD: + case ENC_BFM_64M_BITFIELD: + return ARM64_BFM; + case ENC_BFMLAL_ASIMDELEM_F: + case ENC_BFMLAL_ASIMDSAME2_F_: + return ARM64_BFMLAL; + case ENC_BFMLALB_Z_ZZZ_: + case ENC_BFMLALB_Z_ZZZI_: + return ARM64_BFMLALB; + case ENC_BFMLALT_Z_ZZZ_: + case ENC_BFMLALT_Z_ZZZI_: + return ARM64_BFMLALT; + case ENC_BFMMLA_ASIMDSAME2_E: + case ENC_BFMMLA_Z_ZZZ_: + return ARM64_BFMMLA; + case ENC_BFMOPA_ZA32_PP_ZZ_: + return ARM64_BFMOPA; + case ENC_BFMOPS_ZA32_PP_ZZ_: + return ARM64_BFMOPS; + case ENC_BFXIL_BFM_32M_BITFIELD: + case ENC_BFXIL_BFM_64M_BITFIELD: + return ARM64_BFXIL; + case ENC_BGRP_Z_ZZ_: + return ARM64_BGRP; + case ENC_BIC_ASIMDIMM_L_HL: + case ENC_BIC_ASIMDIMM_L_SL: + case ENC_BIC_ASIMDSAME_ONLY: + case ENC_BIC_AND_Z_ZI_: + case ENC_BIC_32_LOG_SHIFT: + case ENC_BIC_64_LOG_SHIFT: + case ENC_BIC_P_P_PP_Z: + case ENC_BIC_Z_P_ZZ_: + case ENC_BIC_Z_ZZ_: + return ARM64_BIC; + case ENC_BICS_32_LOG_SHIFT: + case ENC_BICS_64_LOG_SHIFT: + case ENC_BICS_P_P_PP_Z: + return ARM64_BICS; + case ENC_BIF_ASIMDSAME_ONLY: + return ARM64_BIF; + case ENC_BIT_ASIMDSAME_ONLY: + return ARM64_BIT; + case ENC_BL_ONLY_BRANCH_IMM: + return ARM64_BL; + case ENC_BLR_64_BRANCH_REG: + return ARM64_BLR; + case ENC_BLRAA_64P_BRANCH_REG: + return ARM64_BLRAA; + case ENC_BLRAAZ_64_BRANCH_REG: + return ARM64_BLRAAZ; + case ENC_BLRAB_64P_BRANCH_REG: + return ARM64_BLRAB; + case ENC_BLRABZ_64_BRANCH_REG: + return ARM64_BLRABZ; + case ENC_BR_64_BRANCH_REG: + return ARM64_BR; + case ENC_BRAA_64P_BRANCH_REG: + return ARM64_BRAA; + case ENC_BRAAZ_64_BRANCH_REG: + return ARM64_BRAAZ; + case ENC_BRAB_64P_BRANCH_REG: + return ARM64_BRAB; + case ENC_BRABZ_64_BRANCH_REG: + return ARM64_BRABZ; + case ENC_BRK_EX_EXCEPTION: + return ARM64_BRK; + case ENC_BRKA_P_P_P_: + return ARM64_BRKA; + case ENC_BRKAS_P_P_P_Z: + return ARM64_BRKAS; + case ENC_BRKB_P_P_P_: + return ARM64_BRKB; + case ENC_BRKBS_P_P_P_Z: + return ARM64_BRKBS; + case ENC_BRKN_P_P_PP_: + return ARM64_BRKN; + case ENC_BRKNS_P_P_PP_: + return ARM64_BRKNS; + case ENC_BRKPA_P_P_PP_: + return ARM64_BRKPA; + case ENC_BRKPAS_P_P_PP_: + return ARM64_BRKPAS; + case ENC_BRKPB_P_P_PP_: + return ARM64_BRKPB; + case ENC_BRKPBS_P_P_PP_: + return ARM64_BRKPBS; + case ENC_BSL_ASIMDSAME_ONLY: + case ENC_BSL_Z_ZZZ_: + return ARM64_BSL; + case ENC_BSL1N_Z_ZZZ_: + return ARM64_BSL1N; + case ENC_BSL2N_Z_ZZZ_: + return ARM64_BSL2N; + case ENC_BTI_HB_HINTS: + return ARM64_BTI; + //case ENC_B_ONLY_CONDBRANCH: + // return ARM64_B_AL; + //case ENC_B_ONLY_CONDBRANCH: + // return ARM64_B_CC; + //case ENC_B_ONLY_CONDBRANCH: + // return ARM64_B_CS; + //case ENC_B_ONLY_CONDBRANCH: + // return ARM64_B_EQ; + //case ENC_B_ONLY_CONDBRANCH: + // return ARM64_B_GE; + //case ENC_B_ONLY_CONDBRANCH: + // return ARM64_B_GT; + //case ENC_B_ONLY_CONDBRANCH: + // return ARM64_B_HI; + //case ENC_B_ONLY_CONDBRANCH: + // return ARM64_B_LE; + //case ENC_B_ONLY_CONDBRANCH: + // return ARM64_B_LS; + //case ENC_B_ONLY_CONDBRANCH: + // return ARM64_B_LT; + //case ENC_B_ONLY_CONDBRANCH: + // return ARM64_B_MI; + //case ENC_B_ONLY_CONDBRANCH: + // return ARM64_B_NE; + //case ENC_B_ONLY_CONDBRANCH: + // return ARM64_B_NV; + //case ENC_B_ONLY_CONDBRANCH: + // return ARM64_B_PL; + //case ENC_B_ONLY_CONDBRANCH: + // return ARM64_B_VC; + //case ENC_B_ONLY_CONDBRANCH: + // return ARM64_B_VS; + case ENC_CADD_Z_ZZ_: + return ARM64_CADD; + case ENC_CAS_C32_COMSWAP: + case ENC_CAS_C64_COMSWAP: + return ARM64_CAS; + case ENC_CASA_C32_COMSWAP: + case ENC_CASA_C64_COMSWAP: + return ARM64_CASA; + case ENC_CASAB_C32_COMSWAP: + return ARM64_CASAB; + case ENC_CASAH_C32_COMSWAP: + return ARM64_CASAH; + case ENC_CASAL_C32_COMSWAP: + case ENC_CASAL_C64_COMSWAP: + return ARM64_CASAL; + case ENC_CASALB_C32_COMSWAP: + return ARM64_CASALB; + case ENC_CASALH_C32_COMSWAP: + return ARM64_CASALH; + case ENC_CASB_C32_COMSWAP: + return ARM64_CASB; + case ENC_CASH_C32_COMSWAP: + return ARM64_CASH; + case ENC_CASL_C32_COMSWAP: + case ENC_CASL_C64_COMSWAP: + return ARM64_CASL; + case ENC_CASLB_C32_COMSWAP: + return ARM64_CASLB; + case ENC_CASLH_C32_COMSWAP: + return ARM64_CASLH; + case ENC_CASP_CP32_COMSWAPPR: + case ENC_CASP_CP64_COMSWAPPR: + return ARM64_CASP; + case ENC_CASPA_CP32_COMSWAPPR: + case ENC_CASPA_CP64_COMSWAPPR: + return ARM64_CASPA; + case ENC_CASPAL_CP32_COMSWAPPR: + case ENC_CASPAL_CP64_COMSWAPPR: + return ARM64_CASPAL; + case ENC_CASPL_CP32_COMSWAPPR: + case ENC_CASPL_CP64_COMSWAPPR: + return ARM64_CASPL; + case ENC_CBNZ_32_COMPBRANCH: + case ENC_CBNZ_64_COMPBRANCH: + return ARM64_CBNZ; + case ENC_CBZ_32_COMPBRANCH: + case ENC_CBZ_64_COMPBRANCH: + return ARM64_CBZ; + case ENC_CCMN_32_CONDCMP_IMM: + case ENC_CCMN_64_CONDCMP_IMM: + case ENC_CCMN_32_CONDCMP_REG: + case ENC_CCMN_64_CONDCMP_REG: + return ARM64_CCMN; + case ENC_CCMP_32_CONDCMP_IMM: + case ENC_CCMP_64_CONDCMP_IMM: + case ENC_CCMP_32_CONDCMP_REG: + case ENC_CCMP_64_CONDCMP_REG: + return ARM64_CCMP; + case ENC_CDOT_Z_ZZZ_: + case ENC_CDOT_Z_ZZZI_S: + case ENC_CDOT_Z_ZZZI_D: + return ARM64_CDOT; + case ENC_CFINV_M_PSTATE: + return ARM64_CFINV; + case ENC_CFP_SYS_CR_SYSTEMINSTRS: + return ARM64_CFP; + case ENC_CINC_CSINC_32_CONDSEL: + case ENC_CINC_CSINC_64_CONDSEL: + return ARM64_CINC; + case ENC_CINV_CSINV_32_CONDSEL: + case ENC_CINV_CSINV_64_CONDSEL: + return ARM64_CINV; + case ENC_CLASTA_R_P_Z_: + case ENC_CLASTA_V_P_Z_: + case ENC_CLASTA_Z_P_ZZ_: + return ARM64_CLASTA; + case ENC_CLASTB_R_P_Z_: + case ENC_CLASTB_V_P_Z_: + case ENC_CLASTB_Z_P_ZZ_: + return ARM64_CLASTB; + case ENC_CLREX_BN_BARRIERS: + return ARM64_CLREX; + case ENC_CLS_ASIMDMISC_R: + case ENC_CLS_32_DP_1SRC: + case ENC_CLS_64_DP_1SRC: + case ENC_CLS_Z_P_Z_: + return ARM64_CLS; + case ENC_CLZ_ASIMDMISC_R: + case ENC_CLZ_32_DP_1SRC: + case ENC_CLZ_64_DP_1SRC: + case ENC_CLZ_Z_P_Z_: + return ARM64_CLZ; + case ENC_CMEQ_ASISDSAME_ONLY: + case ENC_CMEQ_ASIMDSAME_ONLY: + case ENC_CMEQ_ASISDMISC_Z: + case ENC_CMEQ_ASIMDMISC_Z: + return ARM64_CMEQ; + case ENC_CMGE_ASISDSAME_ONLY: + case ENC_CMGE_ASIMDSAME_ONLY: + case ENC_CMGE_ASISDMISC_Z: + case ENC_CMGE_ASIMDMISC_Z: + return ARM64_CMGE; + case ENC_CMGT_ASISDSAME_ONLY: + case ENC_CMGT_ASIMDSAME_ONLY: + case ENC_CMGT_ASISDMISC_Z: + case ENC_CMGT_ASIMDMISC_Z: + return ARM64_CMGT; + case ENC_CMHI_ASISDSAME_ONLY: + case ENC_CMHI_ASIMDSAME_ONLY: + return ARM64_CMHI; + case ENC_CMHS_ASISDSAME_ONLY: + case ENC_CMHS_ASIMDSAME_ONLY: + return ARM64_CMHS; + case ENC_CMLA_Z_ZZZ_: + case ENC_CMLA_Z_ZZZI_H: + case ENC_CMLA_Z_ZZZI_S: + return ARM64_CMLA; + case ENC_CMLE_ASISDMISC_Z: + case ENC_CMLE_ASIMDMISC_Z: + return ARM64_CMLE; + case ENC_CMLT_ASISDMISC_Z: + case ENC_CMLT_ASIMDMISC_Z: + return ARM64_CMLT; + case ENC_CMN_ADDS_32S_ADDSUB_EXT: + case ENC_CMN_ADDS_64S_ADDSUB_EXT: + case ENC_CMN_ADDS_32S_ADDSUB_IMM: + case ENC_CMN_ADDS_64S_ADDSUB_IMM: + case ENC_CMN_ADDS_32_ADDSUB_SHIFT: + case ENC_CMN_ADDS_64_ADDSUB_SHIFT: + return ARM64_CMN; + case ENC_CMP_SUBS_32S_ADDSUB_EXT: + case ENC_CMP_SUBS_64S_ADDSUB_EXT: + case ENC_CMP_SUBS_32S_ADDSUB_IMM: + case ENC_CMP_SUBS_64S_ADDSUB_IMM: + case ENC_CMP_SUBS_32_ADDSUB_SHIFT: + case ENC_CMP_SUBS_64_ADDSUB_SHIFT: + return ARM64_CMP; + case ENC_CMPEQ_P_P_ZI_: + case ENC_CMPEQ_P_P_ZW_: + case ENC_CMPEQ_P_P_ZZ_: + return ARM64_CMPEQ; + case ENC_CMPGE_P_P_ZI_: + case ENC_CMPGE_P_P_ZW_: + case ENC_CMPGE_P_P_ZZ_: + return ARM64_CMPGE; + case ENC_CMPGT_P_P_ZI_: + case ENC_CMPGT_P_P_ZW_: + case ENC_CMPGT_P_P_ZZ_: + return ARM64_CMPGT; + case ENC_CMPHI_P_P_ZI_: + case ENC_CMPHI_P_P_ZW_: + case ENC_CMPHI_P_P_ZZ_: + return ARM64_CMPHI; + case ENC_CMPHS_P_P_ZI_: + case ENC_CMPHS_P_P_ZW_: + case ENC_CMPHS_P_P_ZZ_: + return ARM64_CMPHS; + case ENC_CMPLE_CMPGE_P_P_ZZ_: + case ENC_CMPLE_P_P_ZI_: + case ENC_CMPLE_P_P_ZW_: + return ARM64_CMPLE; + case ENC_CMPLO_CMPHI_P_P_ZZ_: + case ENC_CMPLO_P_P_ZI_: + case ENC_CMPLO_P_P_ZW_: + return ARM64_CMPLO; + case ENC_CMPLS_CMPHS_P_P_ZZ_: + case ENC_CMPLS_P_P_ZI_: + case ENC_CMPLS_P_P_ZW_: + return ARM64_CMPLS; + case ENC_CMPLT_CMPGT_P_P_ZZ_: + case ENC_CMPLT_P_P_ZI_: + case ENC_CMPLT_P_P_ZW_: + return ARM64_CMPLT; + case ENC_CMPNE_P_P_ZI_: + case ENC_CMPNE_P_P_ZW_: + case ENC_CMPNE_P_P_ZZ_: + return ARM64_CMPNE; + case ENC_CMPP_SUBPS_64S_DP_2SRC: + return ARM64_CMPP; + case ENC_CMTST_ASISDSAME_ONLY: + case ENC_CMTST_ASIMDSAME_ONLY: + return ARM64_CMTST; + case ENC_CNEG_CSNEG_32_CONDSEL: + case ENC_CNEG_CSNEG_64_CONDSEL: + return ARM64_CNEG; + case ENC_CNOT_Z_P_Z_: + return ARM64_CNOT; + case ENC_CNT_ASIMDMISC_R: + case ENC_CNT_Z_P_Z_: + return ARM64_CNT; + case ENC_CNTB_R_S_: + return ARM64_CNTB; + case ENC_CNTD_R_S_: + return ARM64_CNTD; + case ENC_CNTH_R_S_: + return ARM64_CNTH; + case ENC_CNTP_R_P_P_: + return ARM64_CNTP; + case ENC_CNTW_R_S_: + return ARM64_CNTW; + case ENC_COMPACT_Z_P_Z_: + return ARM64_COMPACT; + case ENC_CPP_SYS_CR_SYSTEMINSTRS: + return ARM64_CPP; + case ENC_CPY_Z_O_I_: + case ENC_CPY_Z_P_I_: + case ENC_CPY_Z_P_R_: + case ENC_CPY_Z_P_V_: + return ARM64_CPY; + case ENC_CRC32B_32C_DP_2SRC: + return ARM64_CRC32B; + case ENC_CRC32CB_32C_DP_2SRC: + return ARM64_CRC32CB; + case ENC_CRC32CH_32C_DP_2SRC: + return ARM64_CRC32CH; + case ENC_CRC32CW_32C_DP_2SRC: + return ARM64_CRC32CW; + case ENC_CRC32CX_64C_DP_2SRC: + return ARM64_CRC32CX; + case ENC_CRC32H_32C_DP_2SRC: + return ARM64_CRC32H; + case ENC_CRC32W_32C_DP_2SRC: + return ARM64_CRC32W; + case ENC_CRC32X_64C_DP_2SRC: + return ARM64_CRC32X; + case ENC_CSDB_HI_HINTS: + return ARM64_CSDB; + case ENC_CSEL_32_CONDSEL: + case ENC_CSEL_64_CONDSEL: + return ARM64_CSEL; + case ENC_CSET_CSINC_32_CONDSEL: + case ENC_CSET_CSINC_64_CONDSEL: + return ARM64_CSET; + case ENC_CSETM_CSINV_32_CONDSEL: + case ENC_CSETM_CSINV_64_CONDSEL: + return ARM64_CSETM; + case ENC_CSINC_32_CONDSEL: + case ENC_CSINC_64_CONDSEL: + return ARM64_CSINC; + case ENC_CSINV_32_CONDSEL: + case ENC_CSINV_64_CONDSEL: + return ARM64_CSINV; + case ENC_CSNEG_32_CONDSEL: + case ENC_CSNEG_64_CONDSEL: + return ARM64_CSNEG; + case ENC_CTERMEQ_RR_: + return ARM64_CTERMEQ; + case ENC_CTERMNE_RR_: + return ARM64_CTERMNE; + case ENC_DC_SYS_CR_SYSTEMINSTRS: + return ARM64_DC; + case ENC_DCPS1_DC_EXCEPTION: + return ARM64_DCPS1; + case ENC_DCPS2_DC_EXCEPTION: + return ARM64_DCPS2; + case ENC_DCPS3_DC_EXCEPTION: + return ARM64_DCPS3; + case ENC_DECB_R_RS_: + return ARM64_DECB; + case ENC_DECD_R_RS_: + case ENC_DECD_Z_ZS_: + return ARM64_DECD; + case ENC_DECH_R_RS_: + case ENC_DECH_Z_ZS_: + return ARM64_DECH; + case ENC_DECP_R_P_R_: + case ENC_DECP_Z_P_Z_: + return ARM64_DECP; + case ENC_DECW_R_RS_: + case ENC_DECW_Z_ZS_: + return ARM64_DECW; + case ENC_DGH_HI_HINTS: + return ARM64_DGH; + case ENC_DMB_BO_BARRIERS: + return ARM64_DMB; + case ENC_DRPS_64E_BRANCH_REG: + return ARM64_DRPS; + case ENC_DSB_BO_BARRIERS: + case ENC_DSB_BON_BARRIERS: + return ARM64_DSB; + case ENC_DUP_ASISDONE_ONLY: + case ENC_DUP_ASIMDINS_DV_V: + case ENC_DUP_ASIMDINS_DR_R: + case ENC_DUP_P_P_PI_: + case ENC_DUP_Z_I_: + case ENC_DUP_Z_R_: + case ENC_DUP_Z_ZI_: + return ARM64_DUP; + case ENC_DUPM_Z_I_: + return ARM64_DUPM; + case ENC_DVP_SYS_CR_SYSTEMINSTRS: + return ARM64_DVP; + case ENC_EON_32_LOG_SHIFT: + case ENC_EON_64_LOG_SHIFT: + case ENC_EON_EOR_Z_ZI_: + return ARM64_EON; + case ENC_EOR_ASIMDSAME_ONLY: + case ENC_EOR_32_LOG_IMM: + case ENC_EOR_64_LOG_IMM: + case ENC_EOR_32_LOG_SHIFT: + case ENC_EOR_64_LOG_SHIFT: + case ENC_EOR_P_P_PP_Z: + case ENC_EOR_Z_P_ZZ_: + case ENC_EOR_Z_ZI_: + case ENC_EOR_Z_ZZ_: + return ARM64_EOR; + case ENC_EOR3_VVV16_CRYPTO4: + case ENC_EOR3_Z_ZZZ_: + return ARM64_EOR3; + case ENC_EORBT_Z_ZZ_: + return ARM64_EORBT; + case ENC_EORS_P_P_PP_Z: + return ARM64_EORS; + case ENC_EORTB_Z_ZZ_: + return ARM64_EORTB; + case ENC_EORV_R_P_Z_: + return ARM64_EORV; + case ENC_ERET_64E_BRANCH_REG: + return ARM64_ERET; + case ENC_ERETAA_64E_BRANCH_REG: + return ARM64_ERETAA; + case ENC_ERETAB_64E_BRANCH_REG: + return ARM64_ERETAB; + case ENC_ESB_HI_HINTS: + return ARM64_ESB; + case ENC_EXT_ASIMDEXT_ONLY: + case ENC_EXT_Z_ZI_CON: + case ENC_EXT_Z_ZI_DES: + return ARM64_EXT; + case ENC_EXTR_32_EXTRACT: + case ENC_EXTR_64_EXTRACT: + return ARM64_EXTR; + case ENC_FABD_ASISDSAMEFP16_ONLY: + case ENC_FABD_ASISDSAME_ONLY: + case ENC_FABD_ASIMDSAMEFP16_ONLY: + case ENC_FABD_ASIMDSAME_ONLY: + case ENC_FABD_Z_P_ZZ_: + return ARM64_FABD; + case ENC_FABS_ASIMDMISCFP16_R: + case ENC_FABS_ASIMDMISC_R: + case ENC_FABS_H_FLOATDP1: + case ENC_FABS_S_FLOATDP1: + case ENC_FABS_D_FLOATDP1: + case ENC_FABS_Z_P_Z_: + return ARM64_FABS; + case ENC_FACGE_ASISDSAMEFP16_ONLY: + case ENC_FACGE_ASISDSAME_ONLY: + case ENC_FACGE_ASIMDSAMEFP16_ONLY: + case ENC_FACGE_ASIMDSAME_ONLY: + case ENC_FACGE_P_P_ZZ_: + return ARM64_FACGE; + case ENC_FACGT_ASISDSAMEFP16_ONLY: + case ENC_FACGT_ASISDSAME_ONLY: + case ENC_FACGT_ASIMDSAMEFP16_ONLY: + case ENC_FACGT_ASIMDSAME_ONLY: + case ENC_FACGT_P_P_ZZ_: + return ARM64_FACGT; + case ENC_FACLE_FACGE_P_P_ZZ_: + return ARM64_FACLE; + case ENC_FACLT_FACGT_P_P_ZZ_: + return ARM64_FACLT; + case ENC_FADD_ASIMDSAMEFP16_ONLY: + case ENC_FADD_ASIMDSAME_ONLY: + case ENC_FADD_H_FLOATDP2: + case ENC_FADD_S_FLOATDP2: + case ENC_FADD_D_FLOATDP2: + case ENC_FADD_Z_P_ZS_: + case ENC_FADD_Z_P_ZZ_: + case ENC_FADD_Z_ZZ_: + return ARM64_FADD; + case ENC_FADDA_V_P_Z_: + return ARM64_FADDA; + case ENC_FADDP_ASISDPAIR_ONLY_H: + case ENC_FADDP_ASISDPAIR_ONLY_SD: + case ENC_FADDP_ASIMDSAMEFP16_ONLY: + case ENC_FADDP_ASIMDSAME_ONLY: + case ENC_FADDP_Z_P_ZZ_: + return ARM64_FADDP; + case ENC_FADDV_V_P_Z_: + return ARM64_FADDV; + case ENC_FCADD_ASIMDSAME2_C: + case ENC_FCADD_Z_P_ZZ_: + return ARM64_FCADD; + case ENC_FCCMP_H_FLOATCCMP: + case ENC_FCCMP_S_FLOATCCMP: + case ENC_FCCMP_D_FLOATCCMP: + return ARM64_FCCMP; + case ENC_FCCMPE_H_FLOATCCMP: + case ENC_FCCMPE_S_FLOATCCMP: + case ENC_FCCMPE_D_FLOATCCMP: + return ARM64_FCCMPE; + case ENC_FCMEQ_ASISDSAMEFP16_ONLY: + case ENC_FCMEQ_ASISDSAME_ONLY: + case ENC_FCMEQ_ASIMDSAMEFP16_ONLY: + case ENC_FCMEQ_ASIMDSAME_ONLY: + case ENC_FCMEQ_ASISDMISCFP16_FZ: + case ENC_FCMEQ_ASISDMISC_FZ: + case ENC_FCMEQ_ASIMDMISCFP16_FZ: + case ENC_FCMEQ_ASIMDMISC_FZ: + case ENC_FCMEQ_P_P_Z0_: + case ENC_FCMEQ_P_P_ZZ_: + return ARM64_FCMEQ; + case ENC_FCMGE_ASISDSAMEFP16_ONLY: + case ENC_FCMGE_ASISDSAME_ONLY: + case ENC_FCMGE_ASIMDSAMEFP16_ONLY: + case ENC_FCMGE_ASIMDSAME_ONLY: + case ENC_FCMGE_ASISDMISCFP16_FZ: + case ENC_FCMGE_ASISDMISC_FZ: + case ENC_FCMGE_ASIMDMISCFP16_FZ: + case ENC_FCMGE_ASIMDMISC_FZ: + case ENC_FCMGE_P_P_Z0_: + case ENC_FCMGE_P_P_ZZ_: + return ARM64_FCMGE; + case ENC_FCMGT_ASISDSAMEFP16_ONLY: + case ENC_FCMGT_ASISDSAME_ONLY: + case ENC_FCMGT_ASIMDSAMEFP16_ONLY: + case ENC_FCMGT_ASIMDSAME_ONLY: + case ENC_FCMGT_ASISDMISCFP16_FZ: + case ENC_FCMGT_ASISDMISC_FZ: + case ENC_FCMGT_ASIMDMISCFP16_FZ: + case ENC_FCMGT_ASIMDMISC_FZ: + case ENC_FCMGT_P_P_Z0_: + case ENC_FCMGT_P_P_ZZ_: + return ARM64_FCMGT; + case ENC_FCMLA_ASIMDELEM_C_H: + case ENC_FCMLA_ASIMDELEM_C_S: + case ENC_FCMLA_ASIMDSAME2_C: + case ENC_FCMLA_Z_P_ZZZ_: + case ENC_FCMLA_Z_ZZZI_H: + case ENC_FCMLA_Z_ZZZI_S: + return ARM64_FCMLA; + case ENC_FCMLE_ASISDMISCFP16_FZ: + case ENC_FCMLE_ASISDMISC_FZ: + case ENC_FCMLE_ASIMDMISCFP16_FZ: + case ENC_FCMLE_ASIMDMISC_FZ: + case ENC_FCMLE_FCMGE_P_P_ZZ_: + case ENC_FCMLE_P_P_Z0_: + return ARM64_FCMLE; + case ENC_FCMLT_ASISDMISCFP16_FZ: + case ENC_FCMLT_ASISDMISC_FZ: + case ENC_FCMLT_ASIMDMISCFP16_FZ: + case ENC_FCMLT_ASIMDMISC_FZ: + case ENC_FCMLT_FCMGT_P_P_ZZ_: + case ENC_FCMLT_P_P_Z0_: + return ARM64_FCMLT; + case ENC_FCMNE_P_P_Z0_: + case ENC_FCMNE_P_P_ZZ_: + return ARM64_FCMNE; + case ENC_FCMP_H_FLOATCMP: + case ENC_FCMP_HZ_FLOATCMP: + case ENC_FCMP_S_FLOATCMP: + case ENC_FCMP_SZ_FLOATCMP: + case ENC_FCMP_D_FLOATCMP: + case ENC_FCMP_DZ_FLOATCMP: + return ARM64_FCMP; + case ENC_FCMPE_H_FLOATCMP: + case ENC_FCMPE_HZ_FLOATCMP: + case ENC_FCMPE_S_FLOATCMP: + case ENC_FCMPE_SZ_FLOATCMP: + case ENC_FCMPE_D_FLOATCMP: + case ENC_FCMPE_DZ_FLOATCMP: + return ARM64_FCMPE; + case ENC_FCMUO_P_P_ZZ_: + return ARM64_FCMUO; + case ENC_FCPY_Z_P_I_: + return ARM64_FCPY; + case ENC_FCSEL_H_FLOATSEL: + case ENC_FCSEL_S_FLOATSEL: + case ENC_FCSEL_D_FLOATSEL: + return ARM64_FCSEL; + case ENC_FCVT_SH_FLOATDP1: + case ENC_FCVT_DH_FLOATDP1: + case ENC_FCVT_HS_FLOATDP1: + case ENC_FCVT_DS_FLOATDP1: + case ENC_FCVT_HD_FLOATDP1: + case ENC_FCVT_SD_FLOATDP1: + case ENC_FCVT_Z_P_Z_H2S: + case ENC_FCVT_Z_P_Z_H2D: + case ENC_FCVT_Z_P_Z_S2H: + case ENC_FCVT_Z_P_Z_S2D: + case ENC_FCVT_Z_P_Z_D2H: + case ENC_FCVT_Z_P_Z_D2S: + return ARM64_FCVT; + case ENC_FCVTAS_ASISDMISCFP16_R: + case ENC_FCVTAS_ASISDMISC_R: + case ENC_FCVTAS_ASIMDMISCFP16_R: + case ENC_FCVTAS_ASIMDMISC_R: + case ENC_FCVTAS_32H_FLOAT2INT: + case ENC_FCVTAS_64H_FLOAT2INT: + case ENC_FCVTAS_32S_FLOAT2INT: + case ENC_FCVTAS_64S_FLOAT2INT: + case ENC_FCVTAS_32D_FLOAT2INT: + case ENC_FCVTAS_64D_FLOAT2INT: + return ARM64_FCVTAS; + case ENC_FCVTAU_ASISDMISCFP16_R: + case ENC_FCVTAU_ASISDMISC_R: + case ENC_FCVTAU_ASIMDMISCFP16_R: + case ENC_FCVTAU_ASIMDMISC_R: + case ENC_FCVTAU_32H_FLOAT2INT: + case ENC_FCVTAU_64H_FLOAT2INT: + case ENC_FCVTAU_32S_FLOAT2INT: + case ENC_FCVTAU_64S_FLOAT2INT: + case ENC_FCVTAU_32D_FLOAT2INT: + case ENC_FCVTAU_64D_FLOAT2INT: + return ARM64_FCVTAU; + case ENC_FCVTL_ASIMDMISC_L: + return ARM64_FCVTL; + //case ENC_FCVTL_ASIMDMISC_L: + // return ARM64_FCVTL2; + case ENC_FCVTLT_Z_P_Z_H2S: + case ENC_FCVTLT_Z_P_Z_S2D: + return ARM64_FCVTLT; + case ENC_FCVTMS_ASISDMISCFP16_R: + case ENC_FCVTMS_ASISDMISC_R: + case ENC_FCVTMS_ASIMDMISCFP16_R: + case ENC_FCVTMS_ASIMDMISC_R: + case ENC_FCVTMS_32H_FLOAT2INT: + case ENC_FCVTMS_64H_FLOAT2INT: + case ENC_FCVTMS_32S_FLOAT2INT: + case ENC_FCVTMS_64S_FLOAT2INT: + case ENC_FCVTMS_32D_FLOAT2INT: + case ENC_FCVTMS_64D_FLOAT2INT: + return ARM64_FCVTMS; + case ENC_FCVTMU_ASISDMISCFP16_R: + case ENC_FCVTMU_ASISDMISC_R: + case ENC_FCVTMU_ASIMDMISCFP16_R: + case ENC_FCVTMU_ASIMDMISC_R: + case ENC_FCVTMU_32H_FLOAT2INT: + case ENC_FCVTMU_64H_FLOAT2INT: + case ENC_FCVTMU_32S_FLOAT2INT: + case ENC_FCVTMU_64S_FLOAT2INT: + case ENC_FCVTMU_32D_FLOAT2INT: + case ENC_FCVTMU_64D_FLOAT2INT: + return ARM64_FCVTMU; + case ENC_FCVTN_ASIMDMISC_N: + return ARM64_FCVTN; + //case ENC_FCVTN_ASIMDMISC_N: + // return ARM64_FCVTN2; + case ENC_FCVTNS_ASISDMISCFP16_R: + case ENC_FCVTNS_ASISDMISC_R: + case ENC_FCVTNS_ASIMDMISCFP16_R: + case ENC_FCVTNS_ASIMDMISC_R: + case ENC_FCVTNS_32H_FLOAT2INT: + case ENC_FCVTNS_64H_FLOAT2INT: + case ENC_FCVTNS_32S_FLOAT2INT: + case ENC_FCVTNS_64S_FLOAT2INT: + case ENC_FCVTNS_32D_FLOAT2INT: + case ENC_FCVTNS_64D_FLOAT2INT: + return ARM64_FCVTNS; + case ENC_FCVTNT_Z_P_Z_S2H: + case ENC_FCVTNT_Z_P_Z_D2S: + return ARM64_FCVTNT; + case ENC_FCVTNU_ASISDMISCFP16_R: + case ENC_FCVTNU_ASISDMISC_R: + case ENC_FCVTNU_ASIMDMISCFP16_R: + case ENC_FCVTNU_ASIMDMISC_R: + case ENC_FCVTNU_32H_FLOAT2INT: + case ENC_FCVTNU_64H_FLOAT2INT: + case ENC_FCVTNU_32S_FLOAT2INT: + case ENC_FCVTNU_64S_FLOAT2INT: + case ENC_FCVTNU_32D_FLOAT2INT: + case ENC_FCVTNU_64D_FLOAT2INT: + return ARM64_FCVTNU; + case ENC_FCVTPS_ASISDMISCFP16_R: + case ENC_FCVTPS_ASISDMISC_R: + case ENC_FCVTPS_ASIMDMISCFP16_R: + case ENC_FCVTPS_ASIMDMISC_R: + case ENC_FCVTPS_32H_FLOAT2INT: + case ENC_FCVTPS_64H_FLOAT2INT: + case ENC_FCVTPS_32S_FLOAT2INT: + case ENC_FCVTPS_64S_FLOAT2INT: + case ENC_FCVTPS_32D_FLOAT2INT: + case ENC_FCVTPS_64D_FLOAT2INT: + return ARM64_FCVTPS; + case ENC_FCVTPU_ASISDMISCFP16_R: + case ENC_FCVTPU_ASISDMISC_R: + case ENC_FCVTPU_ASIMDMISCFP16_R: + case ENC_FCVTPU_ASIMDMISC_R: + case ENC_FCVTPU_32H_FLOAT2INT: + case ENC_FCVTPU_64H_FLOAT2INT: + case ENC_FCVTPU_32S_FLOAT2INT: + case ENC_FCVTPU_64S_FLOAT2INT: + case ENC_FCVTPU_32D_FLOAT2INT: + case ENC_FCVTPU_64D_FLOAT2INT: + return ARM64_FCVTPU; + case ENC_FCVTX_Z_P_Z_D2S: + return ARM64_FCVTX; + case ENC_FCVTXN_ASISDMISC_N: + case ENC_FCVTXN_ASIMDMISC_N: + return ARM64_FCVTXN; + //case ENC_FCVTXN_ASIMDMISC_N: + // return ARM64_FCVTXN2; + case ENC_FCVTXNT_Z_P_Z_D2S: + return ARM64_FCVTXNT; + case ENC_FCVTZS_ASISDSHF_C: + case ENC_FCVTZS_ASIMDSHF_C: + case ENC_FCVTZS_ASISDMISCFP16_R: + case ENC_FCVTZS_ASISDMISC_R: + case ENC_FCVTZS_ASIMDMISCFP16_R: + case ENC_FCVTZS_ASIMDMISC_R: + case ENC_FCVTZS_32H_FLOAT2FIX: + case ENC_FCVTZS_64H_FLOAT2FIX: + case ENC_FCVTZS_32S_FLOAT2FIX: + case ENC_FCVTZS_64S_FLOAT2FIX: + case ENC_FCVTZS_32D_FLOAT2FIX: + case ENC_FCVTZS_64D_FLOAT2FIX: + case ENC_FCVTZS_32H_FLOAT2INT: + case ENC_FCVTZS_64H_FLOAT2INT: + case ENC_FCVTZS_32S_FLOAT2INT: + case ENC_FCVTZS_64S_FLOAT2INT: + case ENC_FCVTZS_32D_FLOAT2INT: + case ENC_FCVTZS_64D_FLOAT2INT: + case ENC_FCVTZS_Z_P_Z_FP162H: + case ENC_FCVTZS_Z_P_Z_FP162W: + case ENC_FCVTZS_Z_P_Z_FP162X: + case ENC_FCVTZS_Z_P_Z_S2W: + case ENC_FCVTZS_Z_P_Z_S2X: + case ENC_FCVTZS_Z_P_Z_D2W: + case ENC_FCVTZS_Z_P_Z_D2X: + return ARM64_FCVTZS; + case ENC_FCVTZU_ASISDSHF_C: + case ENC_FCVTZU_ASIMDSHF_C: + case ENC_FCVTZU_ASISDMISCFP16_R: + case ENC_FCVTZU_ASISDMISC_R: + case ENC_FCVTZU_ASIMDMISCFP16_R: + case ENC_FCVTZU_ASIMDMISC_R: + case ENC_FCVTZU_32H_FLOAT2FIX: + case ENC_FCVTZU_64H_FLOAT2FIX: + case ENC_FCVTZU_32S_FLOAT2FIX: + case ENC_FCVTZU_64S_FLOAT2FIX: + case ENC_FCVTZU_32D_FLOAT2FIX: + case ENC_FCVTZU_64D_FLOAT2FIX: + case ENC_FCVTZU_32H_FLOAT2INT: + case ENC_FCVTZU_64H_FLOAT2INT: + case ENC_FCVTZU_32S_FLOAT2INT: + case ENC_FCVTZU_64S_FLOAT2INT: + case ENC_FCVTZU_32D_FLOAT2INT: + case ENC_FCVTZU_64D_FLOAT2INT: + case ENC_FCVTZU_Z_P_Z_FP162H: + case ENC_FCVTZU_Z_P_Z_FP162W: + case ENC_FCVTZU_Z_P_Z_FP162X: + case ENC_FCVTZU_Z_P_Z_S2W: + case ENC_FCVTZU_Z_P_Z_S2X: + case ENC_FCVTZU_Z_P_Z_D2W: + case ENC_FCVTZU_Z_P_Z_D2X: + return ARM64_FCVTZU; + case ENC_FDIV_ASIMDSAMEFP16_ONLY: + case ENC_FDIV_ASIMDSAME_ONLY: + case ENC_FDIV_H_FLOATDP2: + case ENC_FDIV_S_FLOATDP2: + case ENC_FDIV_D_FLOATDP2: + case ENC_FDIV_Z_P_ZZ_: + return ARM64_FDIV; + case ENC_FDIVR_Z_P_ZZ_: + return ARM64_FDIVR; + case ENC_FDUP_Z_I_: + return ARM64_FDUP; + case ENC_FEXPA_Z_Z_: + return ARM64_FEXPA; + case ENC_FJCVTZS_32D_FLOAT2INT: + return ARM64_FJCVTZS; + case ENC_FLOGB_Z_P_Z_: + return ARM64_FLOGB; + case ENC_FMAD_Z_P_ZZZ_: + return ARM64_FMAD; + case ENC_FMADD_H_FLOATDP3: + case ENC_FMADD_S_FLOATDP3: + case ENC_FMADD_D_FLOATDP3: + return ARM64_FMADD; + case ENC_FMAX_ASIMDSAMEFP16_ONLY: + case ENC_FMAX_ASIMDSAME_ONLY: + case ENC_FMAX_H_FLOATDP2: + case ENC_FMAX_S_FLOATDP2: + case ENC_FMAX_D_FLOATDP2: + case ENC_FMAX_Z_P_ZS_: + case ENC_FMAX_Z_P_ZZ_: + return ARM64_FMAX; + case ENC_FMAXNM_ASIMDSAMEFP16_ONLY: + case ENC_FMAXNM_ASIMDSAME_ONLY: + case ENC_FMAXNM_H_FLOATDP2: + case ENC_FMAXNM_S_FLOATDP2: + case ENC_FMAXNM_D_FLOATDP2: + case ENC_FMAXNM_Z_P_ZS_: + case ENC_FMAXNM_Z_P_ZZ_: + return ARM64_FMAXNM; + case ENC_FMAXNMP_ASISDPAIR_ONLY_H: + case ENC_FMAXNMP_ASISDPAIR_ONLY_SD: + case ENC_FMAXNMP_ASIMDSAMEFP16_ONLY: + case ENC_FMAXNMP_ASIMDSAME_ONLY: + case ENC_FMAXNMP_Z_P_ZZ_: + return ARM64_FMAXNMP; + case ENC_FMAXNMV_ASIMDALL_ONLY_H: + case ENC_FMAXNMV_ASIMDALL_ONLY_SD: + case ENC_FMAXNMV_V_P_Z_: + return ARM64_FMAXNMV; + case ENC_FMAXP_ASISDPAIR_ONLY_H: + case ENC_FMAXP_ASISDPAIR_ONLY_SD: + case ENC_FMAXP_ASIMDSAMEFP16_ONLY: + case ENC_FMAXP_ASIMDSAME_ONLY: + case ENC_FMAXP_Z_P_ZZ_: + return ARM64_FMAXP; + case ENC_FMAXV_ASIMDALL_ONLY_H: + case ENC_FMAXV_ASIMDALL_ONLY_SD: + case ENC_FMAXV_V_P_Z_: + return ARM64_FMAXV; + case ENC_FMIN_ASIMDSAMEFP16_ONLY: + case ENC_FMIN_ASIMDSAME_ONLY: + case ENC_FMIN_H_FLOATDP2: + case ENC_FMIN_S_FLOATDP2: + case ENC_FMIN_D_FLOATDP2: + case ENC_FMIN_Z_P_ZS_: + case ENC_FMIN_Z_P_ZZ_: + return ARM64_FMIN; + case ENC_FMINNM_ASIMDSAMEFP16_ONLY: + case ENC_FMINNM_ASIMDSAME_ONLY: + case ENC_FMINNM_H_FLOATDP2: + case ENC_FMINNM_S_FLOATDP2: + case ENC_FMINNM_D_FLOATDP2: + case ENC_FMINNM_Z_P_ZS_: + case ENC_FMINNM_Z_P_ZZ_: + return ARM64_FMINNM; + case ENC_FMINNMP_ASISDPAIR_ONLY_H: + case ENC_FMINNMP_ASISDPAIR_ONLY_SD: + case ENC_FMINNMP_ASIMDSAMEFP16_ONLY: + case ENC_FMINNMP_ASIMDSAME_ONLY: + case ENC_FMINNMP_Z_P_ZZ_: + return ARM64_FMINNMP; + case ENC_FMINNMV_ASIMDALL_ONLY_H: + case ENC_FMINNMV_ASIMDALL_ONLY_SD: + case ENC_FMINNMV_V_P_Z_: + return ARM64_FMINNMV; + case ENC_FMINP_ASISDPAIR_ONLY_H: + case ENC_FMINP_ASISDPAIR_ONLY_SD: + case ENC_FMINP_ASIMDSAMEFP16_ONLY: + case ENC_FMINP_ASIMDSAME_ONLY: + case ENC_FMINP_Z_P_ZZ_: + return ARM64_FMINP; + case ENC_FMINV_ASIMDALL_ONLY_H: + case ENC_FMINV_ASIMDALL_ONLY_SD: + case ENC_FMINV_V_P_Z_: + return ARM64_FMINV; + case ENC_FMLA_ASISDELEM_RH_H: + case ENC_FMLA_ASISDELEM_R_SD: + case ENC_FMLA_ASIMDELEM_RH_H: + case ENC_FMLA_ASIMDELEM_R_SD: + case ENC_FMLA_ASIMDSAMEFP16_ONLY: + case ENC_FMLA_ASIMDSAME_ONLY: + case ENC_FMLA_Z_P_ZZZ_: + case ENC_FMLA_Z_ZZZI_H: + case ENC_FMLA_Z_ZZZI_S: + case ENC_FMLA_Z_ZZZI_D: + return ARM64_FMLA; + case ENC_FMLAL_ASIMDELEM_LH: + case ENC_FMLAL_ASIMDSAME_F: + return ARM64_FMLAL; + case ENC_FMLAL2_ASIMDELEM_LH: + case ENC_FMLAL2_ASIMDSAME_F: + return ARM64_FMLAL2; + case ENC_FMLALB_Z_ZZZ_: + case ENC_FMLALB_Z_ZZZI_S: + return ARM64_FMLALB; + case ENC_FMLALT_Z_ZZZ_: + case ENC_FMLALT_Z_ZZZI_S: + return ARM64_FMLALT; + case ENC_FMLS_ASISDELEM_RH_H: + case ENC_FMLS_ASISDELEM_R_SD: + case ENC_FMLS_ASIMDELEM_RH_H: + case ENC_FMLS_ASIMDELEM_R_SD: + case ENC_FMLS_ASIMDSAMEFP16_ONLY: + case ENC_FMLS_ASIMDSAME_ONLY: + case ENC_FMLS_Z_P_ZZZ_: + case ENC_FMLS_Z_ZZZI_H: + case ENC_FMLS_Z_ZZZI_S: + case ENC_FMLS_Z_ZZZI_D: + return ARM64_FMLS; + case ENC_FMLSL_ASIMDELEM_LH: + case ENC_FMLSL_ASIMDSAME_F: + return ARM64_FMLSL; + case ENC_FMLSL2_ASIMDELEM_LH: + case ENC_FMLSL2_ASIMDSAME_F: + return ARM64_FMLSL2; + case ENC_FMLSLB_Z_ZZZ_: + case ENC_FMLSLB_Z_ZZZI_S: + return ARM64_FMLSLB; + case ENC_FMLSLT_Z_ZZZ_: + case ENC_FMLSLT_Z_ZZZI_S: + return ARM64_FMLSLT; + case ENC_FMMLA_Z_ZZZ_S: + case ENC_FMMLA_Z_ZZZ_D: + return ARM64_FMMLA; + case ENC_FMOPA_ZA32_PP_ZZ_16: + case ENC_FMOPA_ZA_PP_ZZ_32: + case ENC_FMOPA_ZA_PP_ZZ_64: + return ARM64_FMOPA; + case ENC_FMOPS_ZA32_PP_ZZ_16: + case ENC_FMOPS_ZA_PP_ZZ_32: + case ENC_FMOPS_ZA_PP_ZZ_64: + return ARM64_FMOPS; + case ENC_FMOV_ASIMDIMM_H_H: + case ENC_FMOV_ASIMDIMM_S_S: + case ENC_FMOV_ASIMDIMM_D2_D: + case ENC_FMOV_CPY_Z_P_I_: + case ENC_FMOV_DUP_Z_I_: + case ENC_FMOV_FCPY_Z_P_I_: + case ENC_FMOV_FDUP_Z_I_: + case ENC_FMOV_H_FLOATDP1: + case ENC_FMOV_S_FLOATDP1: + case ENC_FMOV_D_FLOATDP1: + case ENC_FMOV_32H_FLOAT2INT: + case ENC_FMOV_64H_FLOAT2INT: + case ENC_FMOV_H32_FLOAT2INT: + case ENC_FMOV_S32_FLOAT2INT: + case ENC_FMOV_32S_FLOAT2INT: + case ENC_FMOV_H64_FLOAT2INT: + case ENC_FMOV_D64_FLOAT2INT: + case ENC_FMOV_V64I_FLOAT2INT: + case ENC_FMOV_64D_FLOAT2INT: + case ENC_FMOV_64VX_FLOAT2INT: + case ENC_FMOV_H_FLOATIMM: + case ENC_FMOV_S_FLOATIMM: + case ENC_FMOV_D_FLOATIMM: + return ARM64_FMOV; + case ENC_FMSB_Z_P_ZZZ_: + return ARM64_FMSB; + case ENC_FMSUB_H_FLOATDP3: + case ENC_FMSUB_S_FLOATDP3: + case ENC_FMSUB_D_FLOATDP3: + return ARM64_FMSUB; + case ENC_FMUL_ASISDELEM_RH_H: + case ENC_FMUL_ASISDELEM_R_SD: + case ENC_FMUL_ASIMDELEM_RH_H: + case ENC_FMUL_ASIMDELEM_R_SD: + case ENC_FMUL_ASIMDSAMEFP16_ONLY: + case ENC_FMUL_ASIMDSAME_ONLY: + case ENC_FMUL_H_FLOATDP2: + case ENC_FMUL_S_FLOATDP2: + case ENC_FMUL_D_FLOATDP2: + case ENC_FMUL_Z_P_ZS_: + case ENC_FMUL_Z_P_ZZ_: + case ENC_FMUL_Z_ZZ_: + case ENC_FMUL_Z_ZZI_H: + case ENC_FMUL_Z_ZZI_S: + case ENC_FMUL_Z_ZZI_D: + return ARM64_FMUL; + case ENC_FMULX_ASISDELEM_RH_H: + case ENC_FMULX_ASISDELEM_R_SD: + case ENC_FMULX_ASIMDELEM_RH_H: + case ENC_FMULX_ASIMDELEM_R_SD: + case ENC_FMULX_ASISDSAMEFP16_ONLY: + case ENC_FMULX_ASISDSAME_ONLY: + case ENC_FMULX_ASIMDSAMEFP16_ONLY: + case ENC_FMULX_ASIMDSAME_ONLY: + case ENC_FMULX_Z_P_ZZ_: + return ARM64_FMULX; + case ENC_FNEG_ASIMDMISCFP16_R: + case ENC_FNEG_ASIMDMISC_R: + case ENC_FNEG_H_FLOATDP1: + case ENC_FNEG_S_FLOATDP1: + case ENC_FNEG_D_FLOATDP1: + case ENC_FNEG_Z_P_Z_: + return ARM64_FNEG; + case ENC_FNMAD_Z_P_ZZZ_: + return ARM64_FNMAD; + case ENC_FNMADD_H_FLOATDP3: + case ENC_FNMADD_S_FLOATDP3: + case ENC_FNMADD_D_FLOATDP3: + return ARM64_FNMADD; + case ENC_FNMLA_Z_P_ZZZ_: + return ARM64_FNMLA; + case ENC_FNMLS_Z_P_ZZZ_: + return ARM64_FNMLS; + case ENC_FNMSB_Z_P_ZZZ_: + return ARM64_FNMSB; + case ENC_FNMSUB_H_FLOATDP3: + case ENC_FNMSUB_S_FLOATDP3: + case ENC_FNMSUB_D_FLOATDP3: + return ARM64_FNMSUB; + case ENC_FNMUL_H_FLOATDP2: + case ENC_FNMUL_S_FLOATDP2: + case ENC_FNMUL_D_FLOATDP2: + return ARM64_FNMUL; + case ENC_FRECPE_ASISDMISCFP16_R: + case ENC_FRECPE_ASISDMISC_R: + case ENC_FRECPE_ASIMDMISCFP16_R: + case ENC_FRECPE_ASIMDMISC_R: + case ENC_FRECPE_Z_Z_: + return ARM64_FRECPE; + case ENC_FRECPS_ASISDSAMEFP16_ONLY: + case ENC_FRECPS_ASISDSAME_ONLY: + case ENC_FRECPS_ASIMDSAMEFP16_ONLY: + case ENC_FRECPS_ASIMDSAME_ONLY: + case ENC_FRECPS_Z_ZZ_: + return ARM64_FRECPS; + case ENC_FRECPX_ASISDMISCFP16_R: + case ENC_FRECPX_ASISDMISC_R: + case ENC_FRECPX_Z_P_Z_: + return ARM64_FRECPX; + case ENC_FRINT32X_ASIMDMISC_R: + case ENC_FRINT32X_S_FLOATDP1: + case ENC_FRINT32X_D_FLOATDP1: + return ARM64_FRINT32X; + case ENC_FRINT32Z_ASIMDMISC_R: + case ENC_FRINT32Z_S_FLOATDP1: + case ENC_FRINT32Z_D_FLOATDP1: + return ARM64_FRINT32Z; + case ENC_FRINT64X_ASIMDMISC_R: + case ENC_FRINT64X_S_FLOATDP1: + case ENC_FRINT64X_D_FLOATDP1: + return ARM64_FRINT64X; + case ENC_FRINT64Z_ASIMDMISC_R: + case ENC_FRINT64Z_S_FLOATDP1: + case ENC_FRINT64Z_D_FLOATDP1: + return ARM64_FRINT64Z; + case ENC_FRINTA_ASIMDMISCFP16_R: + case ENC_FRINTA_ASIMDMISC_R: + case ENC_FRINTA_H_FLOATDP1: + case ENC_FRINTA_S_FLOATDP1: + case ENC_FRINTA_D_FLOATDP1: + case ENC_FRINTA_Z_P_Z_: + return ARM64_FRINTA; + case ENC_FRINTI_ASIMDMISCFP16_R: + case ENC_FRINTI_ASIMDMISC_R: + case ENC_FRINTI_H_FLOATDP1: + case ENC_FRINTI_S_FLOATDP1: + case ENC_FRINTI_D_FLOATDP1: + case ENC_FRINTI_Z_P_Z_: + return ARM64_FRINTI; + case ENC_FRINTM_ASIMDMISCFP16_R: + case ENC_FRINTM_ASIMDMISC_R: + case ENC_FRINTM_H_FLOATDP1: + case ENC_FRINTM_S_FLOATDP1: + case ENC_FRINTM_D_FLOATDP1: + case ENC_FRINTM_Z_P_Z_: + return ARM64_FRINTM; + case ENC_FRINTN_ASIMDMISCFP16_R: + case ENC_FRINTN_ASIMDMISC_R: + case ENC_FRINTN_H_FLOATDP1: + case ENC_FRINTN_S_FLOATDP1: + case ENC_FRINTN_D_FLOATDP1: + case ENC_FRINTN_Z_P_Z_: + return ARM64_FRINTN; + case ENC_FRINTP_ASIMDMISCFP16_R: + case ENC_FRINTP_ASIMDMISC_R: + case ENC_FRINTP_H_FLOATDP1: + case ENC_FRINTP_S_FLOATDP1: + case ENC_FRINTP_D_FLOATDP1: + case ENC_FRINTP_Z_P_Z_: + return ARM64_FRINTP; + case ENC_FRINTX_ASIMDMISCFP16_R: + case ENC_FRINTX_ASIMDMISC_R: + case ENC_FRINTX_H_FLOATDP1: + case ENC_FRINTX_S_FLOATDP1: + case ENC_FRINTX_D_FLOATDP1: + case ENC_FRINTX_Z_P_Z_: + return ARM64_FRINTX; + case ENC_FRINTZ_ASIMDMISCFP16_R: + case ENC_FRINTZ_ASIMDMISC_R: + case ENC_FRINTZ_H_FLOATDP1: + case ENC_FRINTZ_S_FLOATDP1: + case ENC_FRINTZ_D_FLOATDP1: + case ENC_FRINTZ_Z_P_Z_: + return ARM64_FRINTZ; + case ENC_FRSQRTE_ASISDMISCFP16_R: + case ENC_FRSQRTE_ASISDMISC_R: + case ENC_FRSQRTE_ASIMDMISCFP16_R: + case ENC_FRSQRTE_ASIMDMISC_R: + case ENC_FRSQRTE_Z_Z_: + return ARM64_FRSQRTE; + case ENC_FRSQRTS_ASISDSAMEFP16_ONLY: + case ENC_FRSQRTS_ASISDSAME_ONLY: + case ENC_FRSQRTS_ASIMDSAMEFP16_ONLY: + case ENC_FRSQRTS_ASIMDSAME_ONLY: + case ENC_FRSQRTS_Z_ZZ_: + return ARM64_FRSQRTS; + case ENC_FSCALE_Z_P_ZZ_: + return ARM64_FSCALE; + case ENC_FSQRT_ASIMDMISCFP16_R: + case ENC_FSQRT_ASIMDMISC_R: + case ENC_FSQRT_H_FLOATDP1: + case ENC_FSQRT_S_FLOATDP1: + case ENC_FSQRT_D_FLOATDP1: + case ENC_FSQRT_Z_P_Z_: + return ARM64_FSQRT; + case ENC_FSUB_ASIMDSAMEFP16_ONLY: + case ENC_FSUB_ASIMDSAME_ONLY: + case ENC_FSUB_H_FLOATDP2: + case ENC_FSUB_S_FLOATDP2: + case ENC_FSUB_D_FLOATDP2: + case ENC_FSUB_Z_P_ZS_: + case ENC_FSUB_Z_P_ZZ_: + case ENC_FSUB_Z_ZZ_: + return ARM64_FSUB; + case ENC_FSUBR_Z_P_ZS_: + case ENC_FSUBR_Z_P_ZZ_: + return ARM64_FSUBR; + case ENC_FTMAD_Z_ZZI_: + return ARM64_FTMAD; + case ENC_FTSMUL_Z_ZZ_: + return ARM64_FTSMUL; + case ENC_FTSSEL_Z_ZZ_: + return ARM64_FTSSEL; + case ENC_GMI_64G_DP_2SRC: + return ARM64_GMI; + case ENC_HINT_HM_HINTS: + return ARM64_HINT; + case ENC_HISTCNT_Z_P_ZZ_: + return ARM64_HISTCNT; + case ENC_HISTSEG_Z_ZZ_: + return ARM64_HISTSEG; + case ENC_HLT_EX_EXCEPTION: + return ARM64_HLT; + case ENC_HVC_EX_EXCEPTION: + return ARM64_HVC; + case ENC_IC_SYS_CR_SYSTEMINSTRS: + return ARM64_IC; + case ENC_INCB_R_RS_: + return ARM64_INCB; + case ENC_INCD_R_RS_: + case ENC_INCD_Z_ZS_: + return ARM64_INCD; + case ENC_INCH_R_RS_: + case ENC_INCH_Z_ZS_: + return ARM64_INCH; + case ENC_INCP_R_P_R_: + case ENC_INCP_Z_P_Z_: + return ARM64_INCP; + case ENC_INCW_R_RS_: + case ENC_INCW_Z_ZS_: + return ARM64_INCW; + case ENC_INDEX_Z_II_: + case ENC_INDEX_Z_IR_: + case ENC_INDEX_Z_RI_: + case ENC_INDEX_Z_RR_: + return ARM64_INDEX; + case ENC_INS_ASIMDINS_IV_V: + case ENC_INS_ASIMDINS_IR_R: + return ARM64_INS; + case ENC_INSR_Z_R_: + case ENC_INSR_Z_V_: + return ARM64_INSR; + case ENC_IRG_64I_DP_2SRC: + return ARM64_IRG; + case ENC_ISB_BI_BARRIERS: + return ARM64_ISB; + case ENC_LASTA_R_P_Z_: + case ENC_LASTA_V_P_Z_: + return ARM64_LASTA; + case ENC_LASTB_R_P_Z_: + case ENC_LASTB_V_P_Z_: + return ARM64_LASTB; + case ENC_LD1_ASISDLSE_R1_1V: + case ENC_LD1_ASISDLSE_R2_2V: + case ENC_LD1_ASISDLSE_R3_3V: + case ENC_LD1_ASISDLSE_R4_4V: + case ENC_LD1_ASISDLSEP_I1_I1: + case ENC_LD1_ASISDLSEP_R1_R1: + case ENC_LD1_ASISDLSEP_I2_I2: + case ENC_LD1_ASISDLSEP_R2_R2: + case ENC_LD1_ASISDLSEP_I3_I3: + case ENC_LD1_ASISDLSEP_R3_R3: + case ENC_LD1_ASISDLSEP_I4_I4: + case ENC_LD1_ASISDLSEP_R4_R4: + case ENC_LD1_ASISDLSO_B1_1B: + case ENC_LD1_ASISDLSO_H1_1H: + case ENC_LD1_ASISDLSO_S1_1S: + case ENC_LD1_ASISDLSO_D1_1D: + case ENC_LD1_ASISDLSOP_B1_I1B: + case ENC_LD1_ASISDLSOP_BX1_R1B: + case ENC_LD1_ASISDLSOP_H1_I1H: + case ENC_LD1_ASISDLSOP_HX1_R1H: + case ENC_LD1_ASISDLSOP_S1_I1S: + case ENC_LD1_ASISDLSOP_SX1_R1S: + case ENC_LD1_ASISDLSOP_D1_I1D: + case ENC_LD1_ASISDLSOP_DX1_R1D: + return ARM64_LD1; + case ENC_LD1B_Z_P_AI_S: + case ENC_LD1B_Z_P_AI_D: + case ENC_LD1B_Z_P_BI_U8: + case ENC_LD1B_Z_P_BI_U16: + case ENC_LD1B_Z_P_BI_U32: + case ENC_LD1B_Z_P_BI_U64: + case ENC_LD1B_Z_P_BR_U8: + case ENC_LD1B_Z_P_BR_U16: + case ENC_LD1B_Z_P_BR_U32: + case ENC_LD1B_Z_P_BR_U64: + case ENC_LD1B_Z_P_BZ_D_X32_UNSCALED: + case ENC_LD1B_Z_P_BZ_S_X32_UNSCALED: + case ENC_LD1B_Z_P_BZ_D_64_UNSCALED: + case ENC_LD1B_ZA_P_RRR_: + return ARM64_LD1B; + case ENC_LD1D_Z_P_AI_D: + case ENC_LD1D_Z_P_BI_U64: + case ENC_LD1D_Z_P_BR_U64: + case ENC_LD1D_Z_P_BZ_D_X32_SCALED: + case ENC_LD1D_Z_P_BZ_D_X32_UNSCALED: + case ENC_LD1D_Z_P_BZ_D_64_SCALED: + case ENC_LD1D_Z_P_BZ_D_64_UNSCALED: + case ENC_LD1D_ZA_P_RRR_: + return ARM64_LD1D; + case ENC_LD1H_Z_P_AI_S: + case ENC_LD1H_Z_P_AI_D: + case ENC_LD1H_Z_P_BI_U16: + case ENC_LD1H_Z_P_BI_U32: + case ENC_LD1H_Z_P_BI_U64: + case ENC_LD1H_Z_P_BR_U16: + case ENC_LD1H_Z_P_BR_U32: + case ENC_LD1H_Z_P_BR_U64: + case ENC_LD1H_Z_P_BZ_S_X32_SCALED: + case ENC_LD1H_Z_P_BZ_D_X32_SCALED: + case ENC_LD1H_Z_P_BZ_D_X32_UNSCALED: + case ENC_LD1H_Z_P_BZ_S_X32_UNSCALED: + case ENC_LD1H_Z_P_BZ_D_64_SCALED: + case ENC_LD1H_Z_P_BZ_D_64_UNSCALED: + case ENC_LD1H_ZA_P_RRR_: + return ARM64_LD1H; + case ENC_LD1Q_ZA_P_RRR_: + return ARM64_LD1Q; + case ENC_LD1R_ASISDLSO_R1: + case ENC_LD1R_ASISDLSOP_R1_I: + case ENC_LD1R_ASISDLSOP_RX1_R: + return ARM64_LD1R; + case ENC_LD1RB_Z_P_BI_U8: + case ENC_LD1RB_Z_P_BI_U16: + case ENC_LD1RB_Z_P_BI_U32: + case ENC_LD1RB_Z_P_BI_U64: + return ARM64_LD1RB; + case ENC_LD1RD_Z_P_BI_U64: + return ARM64_LD1RD; + case ENC_LD1RH_Z_P_BI_U16: + case ENC_LD1RH_Z_P_BI_U32: + case ENC_LD1RH_Z_P_BI_U64: + return ARM64_LD1RH; + case ENC_LD1ROB_Z_P_BI_U8: + case ENC_LD1ROB_Z_P_BR_CONTIGUOUS: + return ARM64_LD1ROB; + case ENC_LD1ROD_Z_P_BI_U64: + case ENC_LD1ROD_Z_P_BR_CONTIGUOUS: + return ARM64_LD1ROD; + case ENC_LD1ROH_Z_P_BI_U16: + case ENC_LD1ROH_Z_P_BR_CONTIGUOUS: + return ARM64_LD1ROH; + case ENC_LD1ROW_Z_P_BI_U32: + case ENC_LD1ROW_Z_P_BR_CONTIGUOUS: + return ARM64_LD1ROW; + case ENC_LD1RQB_Z_P_BI_U8: + case ENC_LD1RQB_Z_P_BR_CONTIGUOUS: + return ARM64_LD1RQB; + case ENC_LD1RQD_Z_P_BI_U64: + case ENC_LD1RQD_Z_P_BR_CONTIGUOUS: + return ARM64_LD1RQD; + case ENC_LD1RQH_Z_P_BI_U16: + case ENC_LD1RQH_Z_P_BR_CONTIGUOUS: + return ARM64_LD1RQH; + case ENC_LD1RQW_Z_P_BI_U32: + case ENC_LD1RQW_Z_P_BR_CONTIGUOUS: + return ARM64_LD1RQW; + case ENC_LD1RSB_Z_P_BI_S16: + case ENC_LD1RSB_Z_P_BI_S32: + case ENC_LD1RSB_Z_P_BI_S64: + return ARM64_LD1RSB; + case ENC_LD1RSH_Z_P_BI_S32: + case ENC_LD1RSH_Z_P_BI_S64: + return ARM64_LD1RSH; + case ENC_LD1RSW_Z_P_BI_S64: + return ARM64_LD1RSW; + case ENC_LD1RW_Z_P_BI_U32: + case ENC_LD1RW_Z_P_BI_U64: + return ARM64_LD1RW; + case ENC_LD1SB_Z_P_AI_S: + case ENC_LD1SB_Z_P_AI_D: + case ENC_LD1SB_Z_P_BI_S16: + case ENC_LD1SB_Z_P_BI_S32: + case ENC_LD1SB_Z_P_BI_S64: + case ENC_LD1SB_Z_P_BR_S16: + case ENC_LD1SB_Z_P_BR_S32: + case ENC_LD1SB_Z_P_BR_S64: + case ENC_LD1SB_Z_P_BZ_D_X32_UNSCALED: + case ENC_LD1SB_Z_P_BZ_S_X32_UNSCALED: + case ENC_LD1SB_Z_P_BZ_D_64_UNSCALED: + return ARM64_LD1SB; + case ENC_LD1SH_Z_P_AI_S: + case ENC_LD1SH_Z_P_AI_D: + case ENC_LD1SH_Z_P_BI_S32: + case ENC_LD1SH_Z_P_BI_S64: + case ENC_LD1SH_Z_P_BR_S32: + case ENC_LD1SH_Z_P_BR_S64: + case ENC_LD1SH_Z_P_BZ_S_X32_SCALED: + case ENC_LD1SH_Z_P_BZ_D_X32_SCALED: + case ENC_LD1SH_Z_P_BZ_D_X32_UNSCALED: + case ENC_LD1SH_Z_P_BZ_S_X32_UNSCALED: + case ENC_LD1SH_Z_P_BZ_D_64_SCALED: + case ENC_LD1SH_Z_P_BZ_D_64_UNSCALED: + return ARM64_LD1SH; + case ENC_LD1SW_Z_P_AI_D: + case ENC_LD1SW_Z_P_BI_S64: + case ENC_LD1SW_Z_P_BR_S64: + case ENC_LD1SW_Z_P_BZ_D_X32_SCALED: + case ENC_LD1SW_Z_P_BZ_D_X32_UNSCALED: + case ENC_LD1SW_Z_P_BZ_D_64_SCALED: + case ENC_LD1SW_Z_P_BZ_D_64_UNSCALED: + return ARM64_LD1SW; + case ENC_LD1W_Z_P_AI_S: + case ENC_LD1W_Z_P_AI_D: + case ENC_LD1W_Z_P_BI_U32: + case ENC_LD1W_Z_P_BI_U64: + case ENC_LD1W_Z_P_BR_U32: + case ENC_LD1W_Z_P_BR_U64: + case ENC_LD1W_Z_P_BZ_S_X32_SCALED: + case ENC_LD1W_Z_P_BZ_D_X32_SCALED: + case ENC_LD1W_Z_P_BZ_D_X32_UNSCALED: + case ENC_LD1W_Z_P_BZ_S_X32_UNSCALED: + case ENC_LD1W_Z_P_BZ_D_64_SCALED: + case ENC_LD1W_Z_P_BZ_D_64_UNSCALED: + case ENC_LD1W_ZA_P_RRR_: + return ARM64_LD1W; + case ENC_LD2_ASISDLSE_R2: + case ENC_LD2_ASISDLSEP_I2_I: + case ENC_LD2_ASISDLSEP_R2_R: + case ENC_LD2_ASISDLSO_B2_2B: + case ENC_LD2_ASISDLSO_H2_2H: + case ENC_LD2_ASISDLSO_S2_2S: + case ENC_LD2_ASISDLSO_D2_2D: + case ENC_LD2_ASISDLSOP_B2_I2B: + case ENC_LD2_ASISDLSOP_BX2_R2B: + case ENC_LD2_ASISDLSOP_H2_I2H: + case ENC_LD2_ASISDLSOP_HX2_R2H: + case ENC_LD2_ASISDLSOP_S2_I2S: + case ENC_LD2_ASISDLSOP_SX2_R2S: + case ENC_LD2_ASISDLSOP_D2_I2D: + case ENC_LD2_ASISDLSOP_DX2_R2D: + return ARM64_LD2; + case ENC_LD2B_Z_P_BI_CONTIGUOUS: + case ENC_LD2B_Z_P_BR_CONTIGUOUS: + return ARM64_LD2B; + case ENC_LD2D_Z_P_BI_CONTIGUOUS: + case ENC_LD2D_Z_P_BR_CONTIGUOUS: + return ARM64_LD2D; + case ENC_LD2H_Z_P_BI_CONTIGUOUS: + case ENC_LD2H_Z_P_BR_CONTIGUOUS: + return ARM64_LD2H; + case ENC_LD2R_ASISDLSO_R2: + case ENC_LD2R_ASISDLSOP_R2_I: + case ENC_LD2R_ASISDLSOP_RX2_R: + return ARM64_LD2R; + case ENC_LD2W_Z_P_BI_CONTIGUOUS: + case ENC_LD2W_Z_P_BR_CONTIGUOUS: + return ARM64_LD2W; + case ENC_LD3_ASISDLSE_R3: + case ENC_LD3_ASISDLSEP_I3_I: + case ENC_LD3_ASISDLSEP_R3_R: + case ENC_LD3_ASISDLSO_B3_3B: + case ENC_LD3_ASISDLSO_H3_3H: + case ENC_LD3_ASISDLSO_S3_3S: + case ENC_LD3_ASISDLSO_D3_3D: + case ENC_LD3_ASISDLSOP_B3_I3B: + case ENC_LD3_ASISDLSOP_BX3_R3B: + case ENC_LD3_ASISDLSOP_H3_I3H: + case ENC_LD3_ASISDLSOP_HX3_R3H: + case ENC_LD3_ASISDLSOP_S3_I3S: + case ENC_LD3_ASISDLSOP_SX3_R3S: + case ENC_LD3_ASISDLSOP_D3_I3D: + case ENC_LD3_ASISDLSOP_DX3_R3D: + return ARM64_LD3; + case ENC_LD3B_Z_P_BI_CONTIGUOUS: + case ENC_LD3B_Z_P_BR_CONTIGUOUS: + return ARM64_LD3B; + case ENC_LD3D_Z_P_BI_CONTIGUOUS: + case ENC_LD3D_Z_P_BR_CONTIGUOUS: + return ARM64_LD3D; + case ENC_LD3H_Z_P_BI_CONTIGUOUS: + case ENC_LD3H_Z_P_BR_CONTIGUOUS: + return ARM64_LD3H; + case ENC_LD3R_ASISDLSO_R3: + case ENC_LD3R_ASISDLSOP_R3_I: + case ENC_LD3R_ASISDLSOP_RX3_R: + return ARM64_LD3R; + case ENC_LD3W_Z_P_BI_CONTIGUOUS: + case ENC_LD3W_Z_P_BR_CONTIGUOUS: + return ARM64_LD3W; + case ENC_LD4_ASISDLSE_R4: + case ENC_LD4_ASISDLSEP_I4_I: + case ENC_LD4_ASISDLSEP_R4_R: + case ENC_LD4_ASISDLSO_B4_4B: + case ENC_LD4_ASISDLSO_H4_4H: + case ENC_LD4_ASISDLSO_S4_4S: + case ENC_LD4_ASISDLSO_D4_4D: + case ENC_LD4_ASISDLSOP_B4_I4B: + case ENC_LD4_ASISDLSOP_BX4_R4B: + case ENC_LD4_ASISDLSOP_H4_I4H: + case ENC_LD4_ASISDLSOP_HX4_R4H: + case ENC_LD4_ASISDLSOP_S4_I4S: + case ENC_LD4_ASISDLSOP_SX4_R4S: + case ENC_LD4_ASISDLSOP_D4_I4D: + case ENC_LD4_ASISDLSOP_DX4_R4D: + return ARM64_LD4; + case ENC_LD4B_Z_P_BI_CONTIGUOUS: + case ENC_LD4B_Z_P_BR_CONTIGUOUS: + return ARM64_LD4B; + case ENC_LD4D_Z_P_BI_CONTIGUOUS: + case ENC_LD4D_Z_P_BR_CONTIGUOUS: + return ARM64_LD4D; + case ENC_LD4H_Z_P_BI_CONTIGUOUS: + case ENC_LD4H_Z_P_BR_CONTIGUOUS: + return ARM64_LD4H; + case ENC_LD4R_ASISDLSO_R4: + case ENC_LD4R_ASISDLSOP_R4_I: + case ENC_LD4R_ASISDLSOP_RX4_R: + return ARM64_LD4R; + case ENC_LD4W_Z_P_BI_CONTIGUOUS: + case ENC_LD4W_Z_P_BR_CONTIGUOUS: + return ARM64_LD4W; + case ENC_LD64B_64L_MEMOP: + return ARM64_LD64B; + case ENC_LDADD_32_MEMOP: + case ENC_LDADD_64_MEMOP: + return ARM64_LDADD; + case ENC_LDADDA_32_MEMOP: + case ENC_LDADDA_64_MEMOP: + return ARM64_LDADDA; + case ENC_LDADDAB_32_MEMOP: + return ARM64_LDADDAB; + case ENC_LDADDAH_32_MEMOP: + return ARM64_LDADDAH; + case ENC_LDADDAL_32_MEMOP: + case ENC_LDADDAL_64_MEMOP: + return ARM64_LDADDAL; + case ENC_LDADDALB_32_MEMOP: + return ARM64_LDADDALB; + case ENC_LDADDALH_32_MEMOP: + return ARM64_LDADDALH; + case ENC_LDADDB_32_MEMOP: + return ARM64_LDADDB; + case ENC_LDADDH_32_MEMOP: + return ARM64_LDADDH; + case ENC_LDADDL_32_MEMOP: + case ENC_LDADDL_64_MEMOP: + return ARM64_LDADDL; + case ENC_LDADDLB_32_MEMOP: + return ARM64_LDADDLB; + case ENC_LDADDLH_32_MEMOP: + return ARM64_LDADDLH; + case ENC_LDAPR_32L_MEMOP: + case ENC_LDAPR_64L_MEMOP: + return ARM64_LDAPR; + case ENC_LDAPRB_32L_MEMOP: + return ARM64_LDAPRB; + case ENC_LDAPRH_32L_MEMOP: + return ARM64_LDAPRH; + case ENC_LDAPUR_32_LDAPSTL_UNSCALED: + case ENC_LDAPUR_64_LDAPSTL_UNSCALED: + return ARM64_LDAPUR; + case ENC_LDAPURB_32_LDAPSTL_UNSCALED: + return ARM64_LDAPURB; + case ENC_LDAPURH_32_LDAPSTL_UNSCALED: + return ARM64_LDAPURH; + case ENC_LDAPURSB_32_LDAPSTL_UNSCALED: + case ENC_LDAPURSB_64_LDAPSTL_UNSCALED: + return ARM64_LDAPURSB; + case ENC_LDAPURSH_32_LDAPSTL_UNSCALED: + case ENC_LDAPURSH_64_LDAPSTL_UNSCALED: + return ARM64_LDAPURSH; + case ENC_LDAPURSW_64_LDAPSTL_UNSCALED: + return ARM64_LDAPURSW; + case ENC_LDAR_LR32_LDSTORD: + case ENC_LDAR_LR64_LDSTORD: + return ARM64_LDAR; + case ENC_LDARB_LR32_LDSTORD: + return ARM64_LDARB; + case ENC_LDARH_LR32_LDSTORD: + return ARM64_LDARH; + case ENC_LDAXP_LP32_LDSTEXCLP: + case ENC_LDAXP_LP64_LDSTEXCLP: + return ARM64_LDAXP; + case ENC_LDAXR_LR32_LDSTEXCLR: + case ENC_LDAXR_LR64_LDSTEXCLR: + return ARM64_LDAXR; + case ENC_LDAXRB_LR32_LDSTEXCLR: + return ARM64_LDAXRB; + case ENC_LDAXRH_LR32_LDSTEXCLR: + return ARM64_LDAXRH; + case ENC_LDCLR_32_MEMOP: + case ENC_LDCLR_64_MEMOP: + return ARM64_LDCLR; + case ENC_LDCLRA_32_MEMOP: + case ENC_LDCLRA_64_MEMOP: + return ARM64_LDCLRA; + case ENC_LDCLRAB_32_MEMOP: + return ARM64_LDCLRAB; + case ENC_LDCLRAH_32_MEMOP: + return ARM64_LDCLRAH; + case ENC_LDCLRAL_32_MEMOP: + case ENC_LDCLRAL_64_MEMOP: + return ARM64_LDCLRAL; + case ENC_LDCLRALB_32_MEMOP: + return ARM64_LDCLRALB; + case ENC_LDCLRALH_32_MEMOP: + return ARM64_LDCLRALH; + case ENC_LDCLRB_32_MEMOP: + return ARM64_LDCLRB; + case ENC_LDCLRH_32_MEMOP: + return ARM64_LDCLRH; + case ENC_LDCLRL_32_MEMOP: + case ENC_LDCLRL_64_MEMOP: + return ARM64_LDCLRL; + case ENC_LDCLRLB_32_MEMOP: + return ARM64_LDCLRLB; + case ENC_LDCLRLH_32_MEMOP: + return ARM64_LDCLRLH; + case ENC_LDEOR_32_MEMOP: + case ENC_LDEOR_64_MEMOP: + return ARM64_LDEOR; + case ENC_LDEORA_32_MEMOP: + case ENC_LDEORA_64_MEMOP: + return ARM64_LDEORA; + case ENC_LDEORAB_32_MEMOP: + return ARM64_LDEORAB; + case ENC_LDEORAH_32_MEMOP: + return ARM64_LDEORAH; + case ENC_LDEORAL_32_MEMOP: + case ENC_LDEORAL_64_MEMOP: + return ARM64_LDEORAL; + case ENC_LDEORALB_32_MEMOP: + return ARM64_LDEORALB; + case ENC_LDEORALH_32_MEMOP: + return ARM64_LDEORALH; + case ENC_LDEORB_32_MEMOP: + return ARM64_LDEORB; + case ENC_LDEORH_32_MEMOP: + return ARM64_LDEORH; + case ENC_LDEORL_32_MEMOP: + case ENC_LDEORL_64_MEMOP: + return ARM64_LDEORL; + case ENC_LDEORLB_32_MEMOP: + return ARM64_LDEORLB; + case ENC_LDEORLH_32_MEMOP: + return ARM64_LDEORLH; + case ENC_LDFF1B_Z_P_AI_S: + case ENC_LDFF1B_Z_P_AI_D: + case ENC_LDFF1B_Z_P_BR_U8: + case ENC_LDFF1B_Z_P_BR_U16: + case ENC_LDFF1B_Z_P_BR_U32: + case ENC_LDFF1B_Z_P_BR_U64: + case ENC_LDFF1B_Z_P_BZ_D_X32_UNSCALED: + case ENC_LDFF1B_Z_P_BZ_S_X32_UNSCALED: + case ENC_LDFF1B_Z_P_BZ_D_64_UNSCALED: + return ARM64_LDFF1B; + case ENC_LDFF1D_Z_P_AI_D: + case ENC_LDFF1D_Z_P_BR_U64: + case ENC_LDFF1D_Z_P_BZ_D_X32_SCALED: + case ENC_LDFF1D_Z_P_BZ_D_X32_UNSCALED: + case ENC_LDFF1D_Z_P_BZ_D_64_SCALED: + case ENC_LDFF1D_Z_P_BZ_D_64_UNSCALED: + return ARM64_LDFF1D; + case ENC_LDFF1H_Z_P_AI_S: + case ENC_LDFF1H_Z_P_AI_D: + case ENC_LDFF1H_Z_P_BR_U16: + case ENC_LDFF1H_Z_P_BR_U32: + case ENC_LDFF1H_Z_P_BR_U64: + case ENC_LDFF1H_Z_P_BZ_S_X32_SCALED: + case ENC_LDFF1H_Z_P_BZ_D_X32_SCALED: + case ENC_LDFF1H_Z_P_BZ_D_X32_UNSCALED: + case ENC_LDFF1H_Z_P_BZ_S_X32_UNSCALED: + case ENC_LDFF1H_Z_P_BZ_D_64_SCALED: + case ENC_LDFF1H_Z_P_BZ_D_64_UNSCALED: + return ARM64_LDFF1H; + case ENC_LDFF1SB_Z_P_AI_S: + case ENC_LDFF1SB_Z_P_AI_D: + case ENC_LDFF1SB_Z_P_BR_S16: + case ENC_LDFF1SB_Z_P_BR_S32: + case ENC_LDFF1SB_Z_P_BR_S64: + case ENC_LDFF1SB_Z_P_BZ_D_X32_UNSCALED: + case ENC_LDFF1SB_Z_P_BZ_S_X32_UNSCALED: + case ENC_LDFF1SB_Z_P_BZ_D_64_UNSCALED: + return ARM64_LDFF1SB; + case ENC_LDFF1SH_Z_P_AI_S: + case ENC_LDFF1SH_Z_P_AI_D: + case ENC_LDFF1SH_Z_P_BR_S32: + case ENC_LDFF1SH_Z_P_BR_S64: + case ENC_LDFF1SH_Z_P_BZ_S_X32_SCALED: + case ENC_LDFF1SH_Z_P_BZ_D_X32_SCALED: + case ENC_LDFF1SH_Z_P_BZ_D_X32_UNSCALED: + case ENC_LDFF1SH_Z_P_BZ_S_X32_UNSCALED: + case ENC_LDFF1SH_Z_P_BZ_D_64_SCALED: + case ENC_LDFF1SH_Z_P_BZ_D_64_UNSCALED: + return ARM64_LDFF1SH; + case ENC_LDFF1SW_Z_P_AI_D: + case ENC_LDFF1SW_Z_P_BR_S64: + case ENC_LDFF1SW_Z_P_BZ_D_X32_SCALED: + case ENC_LDFF1SW_Z_P_BZ_D_X32_UNSCALED: + case ENC_LDFF1SW_Z_P_BZ_D_64_SCALED: + case ENC_LDFF1SW_Z_P_BZ_D_64_UNSCALED: + return ARM64_LDFF1SW; + case ENC_LDFF1W_Z_P_AI_S: + case ENC_LDFF1W_Z_P_AI_D: + case ENC_LDFF1W_Z_P_BR_U32: + case ENC_LDFF1W_Z_P_BR_U64: + case ENC_LDFF1W_Z_P_BZ_S_X32_SCALED: + case ENC_LDFF1W_Z_P_BZ_D_X32_SCALED: + case ENC_LDFF1W_Z_P_BZ_D_X32_UNSCALED: + case ENC_LDFF1W_Z_P_BZ_S_X32_UNSCALED: + case ENC_LDFF1W_Z_P_BZ_D_64_SCALED: + case ENC_LDFF1W_Z_P_BZ_D_64_UNSCALED: + return ARM64_LDFF1W; + case ENC_LDG_64LOFFSET_LDSTTAGS: + return ARM64_LDG; + case ENC_LDGM_64BULK_LDSTTAGS: + return ARM64_LDGM; + case ENC_LDLAR_LR32_LDSTORD: + case ENC_LDLAR_LR64_LDSTORD: + return ARM64_LDLAR; + case ENC_LDLARB_LR32_LDSTORD: + return ARM64_LDLARB; + case ENC_LDLARH_LR32_LDSTORD: + return ARM64_LDLARH; + case ENC_LDNF1B_Z_P_BI_U8: + case ENC_LDNF1B_Z_P_BI_U16: + case ENC_LDNF1B_Z_P_BI_U32: + case ENC_LDNF1B_Z_P_BI_U64: + return ARM64_LDNF1B; + case ENC_LDNF1D_Z_P_BI_U64: + return ARM64_LDNF1D; + case ENC_LDNF1H_Z_P_BI_U16: + case ENC_LDNF1H_Z_P_BI_U32: + case ENC_LDNF1H_Z_P_BI_U64: + return ARM64_LDNF1H; + case ENC_LDNF1SB_Z_P_BI_S16: + case ENC_LDNF1SB_Z_P_BI_S32: + case ENC_LDNF1SB_Z_P_BI_S64: + return ARM64_LDNF1SB; + case ENC_LDNF1SH_Z_P_BI_S32: + case ENC_LDNF1SH_Z_P_BI_S64: + return ARM64_LDNF1SH; + case ENC_LDNF1SW_Z_P_BI_S64: + return ARM64_LDNF1SW; + case ENC_LDNF1W_Z_P_BI_U32: + case ENC_LDNF1W_Z_P_BI_U64: + return ARM64_LDNF1W; + case ENC_LDNP_S_LDSTNAPAIR_OFFS: + case ENC_LDNP_D_LDSTNAPAIR_OFFS: + case ENC_LDNP_Q_LDSTNAPAIR_OFFS: + case ENC_LDNP_32_LDSTNAPAIR_OFFS: + case ENC_LDNP_64_LDSTNAPAIR_OFFS: + return ARM64_LDNP; + case ENC_LDNT1B_Z_P_AR_S_X32_UNSCALED: + case ENC_LDNT1B_Z_P_AR_D_64_UNSCALED: + case ENC_LDNT1B_Z_P_BI_CONTIGUOUS: + case ENC_LDNT1B_Z_P_BR_CONTIGUOUS: + return ARM64_LDNT1B; + case ENC_LDNT1D_Z_P_AR_D_64_UNSCALED: + case ENC_LDNT1D_Z_P_BI_CONTIGUOUS: + case ENC_LDNT1D_Z_P_BR_CONTIGUOUS: + return ARM64_LDNT1D; + case ENC_LDNT1H_Z_P_AR_S_X32_UNSCALED: + case ENC_LDNT1H_Z_P_AR_D_64_UNSCALED: + case ENC_LDNT1H_Z_P_BI_CONTIGUOUS: + case ENC_LDNT1H_Z_P_BR_CONTIGUOUS: + return ARM64_LDNT1H; + case ENC_LDNT1SB_Z_P_AR_S_X32_UNSCALED: + case ENC_LDNT1SB_Z_P_AR_D_64_UNSCALED: + return ARM64_LDNT1SB; + case ENC_LDNT1SH_Z_P_AR_S_X32_UNSCALED: + case ENC_LDNT1SH_Z_P_AR_D_64_UNSCALED: + return ARM64_LDNT1SH; + case ENC_LDNT1SW_Z_P_AR_D_64_UNSCALED: + return ARM64_LDNT1SW; + case ENC_LDNT1W_Z_P_AR_S_X32_UNSCALED: + case ENC_LDNT1W_Z_P_AR_D_64_UNSCALED: + case ENC_LDNT1W_Z_P_BI_CONTIGUOUS: + case ENC_LDNT1W_Z_P_BR_CONTIGUOUS: + return ARM64_LDNT1W; + case ENC_LDP_S_LDSTPAIR_POST: + case ENC_LDP_D_LDSTPAIR_POST: + case ENC_LDP_Q_LDSTPAIR_POST: + case ENC_LDP_S_LDSTPAIR_PRE: + case ENC_LDP_D_LDSTPAIR_PRE: + case ENC_LDP_Q_LDSTPAIR_PRE: + case ENC_LDP_S_LDSTPAIR_OFF: + case ENC_LDP_D_LDSTPAIR_OFF: + case ENC_LDP_Q_LDSTPAIR_OFF: + case ENC_LDP_32_LDSTPAIR_POST: + case ENC_LDP_64_LDSTPAIR_POST: + case ENC_LDP_32_LDSTPAIR_PRE: + case ENC_LDP_64_LDSTPAIR_PRE: + case ENC_LDP_32_LDSTPAIR_OFF: + case ENC_LDP_64_LDSTPAIR_OFF: + return ARM64_LDP; + case ENC_LDPSW_64_LDSTPAIR_POST: + case ENC_LDPSW_64_LDSTPAIR_PRE: + case ENC_LDPSW_64_LDSTPAIR_OFF: + return ARM64_LDPSW; + case ENC_LDR_B_LDST_IMMPOST: + case ENC_LDR_H_LDST_IMMPOST: + case ENC_LDR_S_LDST_IMMPOST: + case ENC_LDR_D_LDST_IMMPOST: + case ENC_LDR_Q_LDST_IMMPOST: + case ENC_LDR_B_LDST_IMMPRE: + case ENC_LDR_H_LDST_IMMPRE: + case ENC_LDR_S_LDST_IMMPRE: + case ENC_LDR_D_LDST_IMMPRE: + case ENC_LDR_Q_LDST_IMMPRE: + case ENC_LDR_B_LDST_POS: + case ENC_LDR_H_LDST_POS: + case ENC_LDR_S_LDST_POS: + case ENC_LDR_D_LDST_POS: + case ENC_LDR_Q_LDST_POS: + case ENC_LDR_32_LDST_IMMPOST: + case ENC_LDR_64_LDST_IMMPOST: + case ENC_LDR_32_LDST_IMMPRE: + case ENC_LDR_64_LDST_IMMPRE: + case ENC_LDR_32_LDST_POS: + case ENC_LDR_64_LDST_POS: + case ENC_LDR_S_LOADLIT: + case ENC_LDR_D_LOADLIT: + case ENC_LDR_Q_LOADLIT: + case ENC_LDR_32_LOADLIT: + case ENC_LDR_64_LOADLIT: + case ENC_LDR_B_LDST_REGOFF: + case ENC_LDR_BL_LDST_REGOFF: + case ENC_LDR_H_LDST_REGOFF: + case ENC_LDR_S_LDST_REGOFF: + case ENC_LDR_D_LDST_REGOFF: + case ENC_LDR_Q_LDST_REGOFF: + case ENC_LDR_32_LDST_REGOFF: + case ENC_LDR_64_LDST_REGOFF: + case ENC_LDR_P_BI_: + case ENC_LDR_Z_BI_: + case ENC_LDR_ZA_RI_: + return ARM64_LDR; + case ENC_LDRAA_64_LDST_PAC: + case ENC_LDRAA_64W_LDST_PAC: + return ARM64_LDRAA; + case ENC_LDRAB_64_LDST_PAC: + case ENC_LDRAB_64W_LDST_PAC: + return ARM64_LDRAB; + case ENC_LDRB_32_LDST_IMMPOST: + case ENC_LDRB_32_LDST_IMMPRE: + case ENC_LDRB_32_LDST_POS: + case ENC_LDRB_32B_LDST_REGOFF: + case ENC_LDRB_32BL_LDST_REGOFF: + return ARM64_LDRB; + case ENC_LDRH_32_LDST_IMMPOST: + case ENC_LDRH_32_LDST_IMMPRE: + case ENC_LDRH_32_LDST_POS: + case ENC_LDRH_32_LDST_REGOFF: + return ARM64_LDRH; + case ENC_LDRSB_32_LDST_IMMPOST: + case ENC_LDRSB_64_LDST_IMMPOST: + case ENC_LDRSB_32_LDST_IMMPRE: + case ENC_LDRSB_64_LDST_IMMPRE: + case ENC_LDRSB_32_LDST_POS: + case ENC_LDRSB_64_LDST_POS: + case ENC_LDRSB_32B_LDST_REGOFF: + case ENC_LDRSB_32BL_LDST_REGOFF: + case ENC_LDRSB_64B_LDST_REGOFF: + case ENC_LDRSB_64BL_LDST_REGOFF: + return ARM64_LDRSB; + case ENC_LDRSH_32_LDST_IMMPOST: + case ENC_LDRSH_64_LDST_IMMPOST: + case ENC_LDRSH_32_LDST_IMMPRE: + case ENC_LDRSH_64_LDST_IMMPRE: + case ENC_LDRSH_32_LDST_POS: + case ENC_LDRSH_64_LDST_POS: + case ENC_LDRSH_32_LDST_REGOFF: + case ENC_LDRSH_64_LDST_REGOFF: + return ARM64_LDRSH; + case ENC_LDRSW_64_LDST_IMMPOST: + case ENC_LDRSW_64_LDST_IMMPRE: + case ENC_LDRSW_64_LDST_POS: + case ENC_LDRSW_64_LOADLIT: + case ENC_LDRSW_64_LDST_REGOFF: + return ARM64_LDRSW; + case ENC_LDSET_32_MEMOP: + case ENC_LDSET_64_MEMOP: + return ARM64_LDSET; + case ENC_LDSETA_32_MEMOP: + case ENC_LDSETA_64_MEMOP: + return ARM64_LDSETA; + case ENC_LDSETAB_32_MEMOP: + return ARM64_LDSETAB; + case ENC_LDSETAH_32_MEMOP: + return ARM64_LDSETAH; + case ENC_LDSETAL_32_MEMOP: + case ENC_LDSETAL_64_MEMOP: + return ARM64_LDSETAL; + case ENC_LDSETALB_32_MEMOP: + return ARM64_LDSETALB; + case ENC_LDSETALH_32_MEMOP: + return ARM64_LDSETALH; + case ENC_LDSETB_32_MEMOP: + return ARM64_LDSETB; + case ENC_LDSETH_32_MEMOP: + return ARM64_LDSETH; + case ENC_LDSETL_32_MEMOP: + case ENC_LDSETL_64_MEMOP: + return ARM64_LDSETL; + case ENC_LDSETLB_32_MEMOP: + return ARM64_LDSETLB; + case ENC_LDSETLH_32_MEMOP: + return ARM64_LDSETLH; + case ENC_LDSMAX_32_MEMOP: + case ENC_LDSMAX_64_MEMOP: + return ARM64_LDSMAX; + case ENC_LDSMAXA_32_MEMOP: + case ENC_LDSMAXA_64_MEMOP: + return ARM64_LDSMAXA; + case ENC_LDSMAXAB_32_MEMOP: + return ARM64_LDSMAXAB; + case ENC_LDSMAXAH_32_MEMOP: + return ARM64_LDSMAXAH; + case ENC_LDSMAXAL_32_MEMOP: + case ENC_LDSMAXAL_64_MEMOP: + return ARM64_LDSMAXAL; + case ENC_LDSMAXALB_32_MEMOP: + return ARM64_LDSMAXALB; + case ENC_LDSMAXALH_32_MEMOP: + return ARM64_LDSMAXALH; + case ENC_LDSMAXB_32_MEMOP: + return ARM64_LDSMAXB; + case ENC_LDSMAXH_32_MEMOP: + return ARM64_LDSMAXH; + case ENC_LDSMAXL_32_MEMOP: + case ENC_LDSMAXL_64_MEMOP: + return ARM64_LDSMAXL; + case ENC_LDSMAXLB_32_MEMOP: + return ARM64_LDSMAXLB; + case ENC_LDSMAXLH_32_MEMOP: + return ARM64_LDSMAXLH; + case ENC_LDSMIN_32_MEMOP: + case ENC_LDSMIN_64_MEMOP: + return ARM64_LDSMIN; + case ENC_LDSMINA_32_MEMOP: + case ENC_LDSMINA_64_MEMOP: + return ARM64_LDSMINA; + case ENC_LDSMINAB_32_MEMOP: + return ARM64_LDSMINAB; + case ENC_LDSMINAH_32_MEMOP: + return ARM64_LDSMINAH; + case ENC_LDSMINAL_32_MEMOP: + case ENC_LDSMINAL_64_MEMOP: + return ARM64_LDSMINAL; + case ENC_LDSMINALB_32_MEMOP: + return ARM64_LDSMINALB; + case ENC_LDSMINALH_32_MEMOP: + return ARM64_LDSMINALH; + case ENC_LDSMINB_32_MEMOP: + return ARM64_LDSMINB; + case ENC_LDSMINH_32_MEMOP: + return ARM64_LDSMINH; + case ENC_LDSMINL_32_MEMOP: + case ENC_LDSMINL_64_MEMOP: + return ARM64_LDSMINL; + case ENC_LDSMINLB_32_MEMOP: + return ARM64_LDSMINLB; + case ENC_LDSMINLH_32_MEMOP: + return ARM64_LDSMINLH; + case ENC_LDTR_32_LDST_UNPRIV: + case ENC_LDTR_64_LDST_UNPRIV: + return ARM64_LDTR; + case ENC_LDTRB_32_LDST_UNPRIV: + return ARM64_LDTRB; + case ENC_LDTRH_32_LDST_UNPRIV: + return ARM64_LDTRH; + case ENC_LDTRSB_32_LDST_UNPRIV: + case ENC_LDTRSB_64_LDST_UNPRIV: + return ARM64_LDTRSB; + case ENC_LDTRSH_32_LDST_UNPRIV: + case ENC_LDTRSH_64_LDST_UNPRIV: + return ARM64_LDTRSH; + case ENC_LDTRSW_64_LDST_UNPRIV: + return ARM64_LDTRSW; + case ENC_LDUMAX_32_MEMOP: + case ENC_LDUMAX_64_MEMOP: + return ARM64_LDUMAX; + case ENC_LDUMAXA_32_MEMOP: + case ENC_LDUMAXA_64_MEMOP: + return ARM64_LDUMAXA; + case ENC_LDUMAXAB_32_MEMOP: + return ARM64_LDUMAXAB; + case ENC_LDUMAXAH_32_MEMOP: + return ARM64_LDUMAXAH; + case ENC_LDUMAXAL_32_MEMOP: + case ENC_LDUMAXAL_64_MEMOP: + return ARM64_LDUMAXAL; + case ENC_LDUMAXALB_32_MEMOP: + return ARM64_LDUMAXALB; + case ENC_LDUMAXALH_32_MEMOP: + return ARM64_LDUMAXALH; + case ENC_LDUMAXB_32_MEMOP: + return ARM64_LDUMAXB; + case ENC_LDUMAXH_32_MEMOP: + return ARM64_LDUMAXH; + case ENC_LDUMAXL_32_MEMOP: + case ENC_LDUMAXL_64_MEMOP: + return ARM64_LDUMAXL; + case ENC_LDUMAXLB_32_MEMOP: + return ARM64_LDUMAXLB; + case ENC_LDUMAXLH_32_MEMOP: + return ARM64_LDUMAXLH; + case ENC_LDUMIN_32_MEMOP: + case ENC_LDUMIN_64_MEMOP: + return ARM64_LDUMIN; + case ENC_LDUMINA_32_MEMOP: + case ENC_LDUMINA_64_MEMOP: + return ARM64_LDUMINA; + case ENC_LDUMINAB_32_MEMOP: + return ARM64_LDUMINAB; + case ENC_LDUMINAH_32_MEMOP: + return ARM64_LDUMINAH; + case ENC_LDUMINAL_32_MEMOP: + case ENC_LDUMINAL_64_MEMOP: + return ARM64_LDUMINAL; + case ENC_LDUMINALB_32_MEMOP: + return ARM64_LDUMINALB; + case ENC_LDUMINALH_32_MEMOP: + return ARM64_LDUMINALH; + case ENC_LDUMINB_32_MEMOP: + return ARM64_LDUMINB; + case ENC_LDUMINH_32_MEMOP: + return ARM64_LDUMINH; + case ENC_LDUMINL_32_MEMOP: + case ENC_LDUMINL_64_MEMOP: + return ARM64_LDUMINL; + case ENC_LDUMINLB_32_MEMOP: + return ARM64_LDUMINLB; + case ENC_LDUMINLH_32_MEMOP: + return ARM64_LDUMINLH; + case ENC_LDUR_B_LDST_UNSCALED: + case ENC_LDUR_H_LDST_UNSCALED: + case ENC_LDUR_S_LDST_UNSCALED: + case ENC_LDUR_D_LDST_UNSCALED: + case ENC_LDUR_Q_LDST_UNSCALED: + case ENC_LDUR_32_LDST_UNSCALED: + case ENC_LDUR_64_LDST_UNSCALED: + return ARM64_LDUR; + case ENC_LDURB_32_LDST_UNSCALED: + return ARM64_LDURB; + case ENC_LDURH_32_LDST_UNSCALED: + return ARM64_LDURH; + case ENC_LDURSB_32_LDST_UNSCALED: + case ENC_LDURSB_64_LDST_UNSCALED: + return ARM64_LDURSB; + case ENC_LDURSH_32_LDST_UNSCALED: + case ENC_LDURSH_64_LDST_UNSCALED: + return ARM64_LDURSH; + case ENC_LDURSW_64_LDST_UNSCALED: + return ARM64_LDURSW; + case ENC_LDXP_LP32_LDSTEXCLP: + case ENC_LDXP_LP64_LDSTEXCLP: + return ARM64_LDXP; + case ENC_LDXR_LR32_LDSTEXCLR: + case ENC_LDXR_LR64_LDSTEXCLR: + return ARM64_LDXR; + case ENC_LDXRB_LR32_LDSTEXCLR: + return ARM64_LDXRB; + case ENC_LDXRH_LR32_LDSTEXCLR: + return ARM64_LDXRH; + case ENC_LSL_LSLV_32_DP_2SRC: + case ENC_LSL_LSLV_64_DP_2SRC: + case ENC_LSL_UBFM_32M_BITFIELD: + case ENC_LSL_UBFM_64M_BITFIELD: + case ENC_LSL_Z_P_ZI_: + case ENC_LSL_Z_P_ZW_: + case ENC_LSL_Z_P_ZZ_: + case ENC_LSL_Z_ZI_: + case ENC_LSL_Z_ZW_: + return ARM64_LSL; + case ENC_LSLR_Z_P_ZZ_: + return ARM64_LSLR; + case ENC_LSLV_32_DP_2SRC: + case ENC_LSLV_64_DP_2SRC: + return ARM64_LSLV; + case ENC_LSR_LSRV_32_DP_2SRC: + case ENC_LSR_LSRV_64_DP_2SRC: + case ENC_LSR_UBFM_32M_BITFIELD: + case ENC_LSR_UBFM_64M_BITFIELD: + case ENC_LSR_Z_P_ZI_: + case ENC_LSR_Z_P_ZW_: + case ENC_LSR_Z_P_ZZ_: + case ENC_LSR_Z_ZI_: + case ENC_LSR_Z_ZW_: + return ARM64_LSR; + case ENC_LSRR_Z_P_ZZ_: + return ARM64_LSRR; + case ENC_LSRV_32_DP_2SRC: + case ENC_LSRV_64_DP_2SRC: + return ARM64_LSRV; + case ENC_MAD_Z_P_ZZZ_: + return ARM64_MAD; + case ENC_MADD_32A_DP_3SRC: + case ENC_MADD_64A_DP_3SRC: + return ARM64_MADD; + case ENC_MATCH_P_P_ZZ_: + return ARM64_MATCH; + case ENC_MLA_ASIMDELEM_R: + case ENC_MLA_ASIMDSAME_ONLY: + case ENC_MLA_Z_P_ZZZ_: + case ENC_MLA_Z_ZZZI_H: + case ENC_MLA_Z_ZZZI_S: + case ENC_MLA_Z_ZZZI_D: + return ARM64_MLA; + case ENC_MLS_ASIMDELEM_R: + case ENC_MLS_ASIMDSAME_ONLY: + case ENC_MLS_Z_P_ZZZ_: + case ENC_MLS_Z_ZZZI_H: + case ENC_MLS_Z_ZZZI_S: + case ENC_MLS_Z_ZZZI_D: + return ARM64_MLS; + case ENC_MNEG_MSUB_32A_DP_3SRC: + case ENC_MNEG_MSUB_64A_DP_3SRC: + return ARM64_MNEG; + case ENC_MOV_ADD_32_ADDSUB_IMM: + case ENC_MOV_ADD_64_ADDSUB_IMM: + case ENC_MOV_DUP_ASISDONE_ONLY: + case ENC_MOV_INS_ASIMDINS_IV_V: + case ENC_MOV_INS_ASIMDINS_IR_R: + case ENC_MOV_MOVN_32_MOVEWIDE: + case ENC_MOV_MOVN_64_MOVEWIDE: + case ENC_MOV_MOVZ_32_MOVEWIDE: + case ENC_MOV_MOVZ_64_MOVEWIDE: + case ENC_MOV_ORR_ASIMDSAME_ONLY: + case ENC_MOV_ORR_32_LOG_IMM: + case ENC_MOV_ORR_64_LOG_IMM: + case ENC_MOV_ORR_32_LOG_SHIFT: + case ENC_MOV_ORR_64_LOG_SHIFT: + case ENC_MOV_UMOV_ASIMDINS_W_W: + case ENC_MOV_UMOV_ASIMDINS_X_X: + case ENC_MOV_AND_P_P_PP_Z: + case ENC_MOV_CPY_Z_O_I_: + case ENC_MOV_CPY_Z_P_I_: + case ENC_MOV_CPY_Z_P_R_: + case ENC_MOV_CPY_Z_P_V_: + case ENC_MOV_DUP_Z_I_: + case ENC_MOV_DUP_Z_R_: + case ENC_MOV_DUP_Z_ZI_: + case ENC_MOV_DUP_Z_ZI_2: + case ENC_MOV_DUPM_Z_I_: + case ENC_MOV_MOVA_Z_P_RZA_B: + case ENC_MOV_MOVA_Z_P_RZA_H: + case ENC_MOV_MOVA_Z_P_RZA_W: + case ENC_MOV_MOVA_Z_P_RZA_D: + case ENC_MOV_MOVA_Z_P_RZA_Q: + case ENC_MOV_MOVA_ZA_P_RZ_B: + case ENC_MOV_MOVA_ZA_P_RZ_H: + case ENC_MOV_MOVA_ZA_P_RZ_W: + case ENC_MOV_MOVA_ZA_P_RZ_D: + case ENC_MOV_MOVA_ZA_P_RZ_Q: + case ENC_MOV_ORR_P_P_PP_Z: + case ENC_MOV_ORR_Z_ZZ_: + case ENC_MOV_SEL_P_P_PP_: + case ENC_MOV_SEL_Z_P_ZZ_: + return ARM64_MOV; + case ENC_MOVA_Z_P_RZA_B: + case ENC_MOVA_Z_P_RZA_H: + case ENC_MOVA_Z_P_RZA_W: + case ENC_MOVA_Z_P_RZA_D: + case ENC_MOVA_Z_P_RZA_Q: + case ENC_MOVA_ZA_P_RZ_B: + case ENC_MOVA_ZA_P_RZ_H: + case ENC_MOVA_ZA_P_RZ_W: + case ENC_MOVA_ZA_P_RZ_D: + case ENC_MOVA_ZA_P_RZ_Q: + return ARM64_MOVA; + case ENC_MOVI_ASIMDIMM_N_B: + case ENC_MOVI_ASIMDIMM_L_HL: + case ENC_MOVI_ASIMDIMM_L_SL: + case ENC_MOVI_ASIMDIMM_M_SM: + case ENC_MOVI_ASIMDIMM_D_DS: + case ENC_MOVI_ASIMDIMM_D2_D: + return ARM64_MOVI; + case ENC_MOVK_32_MOVEWIDE: + case ENC_MOVK_64_MOVEWIDE: + return ARM64_MOVK; + case ENC_MOVN_32_MOVEWIDE: + case ENC_MOVN_64_MOVEWIDE: + return ARM64_MOVN; + case ENC_MOVPRFX_Z_P_Z_: + case ENC_MOVPRFX_Z_Z_: + return ARM64_MOVPRFX; + case ENC_MOVS_ANDS_P_P_PP_Z: + case ENC_MOVS_ORRS_P_P_PP_Z: + return ARM64_MOVS; + case ENC_MOVZ_32_MOVEWIDE: + case ENC_MOVZ_64_MOVEWIDE: + return ARM64_MOVZ; + case ENC_MRS_RS_SYSTEMMOVE: + return ARM64_MRS; + case ENC_MSB_Z_P_ZZZ_: + return ARM64_MSB; + case ENC_MSR_SI_PSTATE: + case ENC_MSR_SR_SYSTEMMOVE: + return ARM64_MSR; + case ENC_MSUB_32A_DP_3SRC: + case ENC_MSUB_64A_DP_3SRC: + return ARM64_MSUB; + case ENC_MUL_MADD_32A_DP_3SRC: + case ENC_MUL_MADD_64A_DP_3SRC: + case ENC_MUL_ASIMDELEM_R: + case ENC_MUL_ASIMDSAME_ONLY: + case ENC_MUL_Z_P_ZZ_: + case ENC_MUL_Z_ZI_: + case ENC_MUL_Z_ZZ_: + case ENC_MUL_Z_ZZI_H: + case ENC_MUL_Z_ZZI_S: + case ENC_MUL_Z_ZZI_D: + return ARM64_MUL; + case ENC_MVN_NOT_ASIMDMISC_R: + case ENC_MVN_ORN_32_LOG_SHIFT: + case ENC_MVN_ORN_64_LOG_SHIFT: + return ARM64_MVN; + case ENC_MVNI_ASIMDIMM_L_HL: + case ENC_MVNI_ASIMDIMM_L_SL: + case ENC_MVNI_ASIMDIMM_M_SM: + return ARM64_MVNI; + case ENC_NAND_P_P_PP_Z: + return ARM64_NAND; + case ENC_NANDS_P_P_PP_Z: + return ARM64_NANDS; + case ENC_NBSL_Z_ZZZ_: + return ARM64_NBSL; + case ENC_NEG_SUB_32_ADDSUB_SHIFT: + case ENC_NEG_SUB_64_ADDSUB_SHIFT: + case ENC_NEG_ASISDMISC_R: + case ENC_NEG_ASIMDMISC_R: + case ENC_NEG_Z_P_Z_: + return ARM64_NEG; + case ENC_NEGS_SUBS_32_ADDSUB_SHIFT: + case ENC_NEGS_SUBS_64_ADDSUB_SHIFT: + return ARM64_NEGS; + case ENC_NGC_SBC_32_ADDSUB_CARRY: + case ENC_NGC_SBC_64_ADDSUB_CARRY: + return ARM64_NGC; + case ENC_NGCS_SBCS_32_ADDSUB_CARRY: + case ENC_NGCS_SBCS_64_ADDSUB_CARRY: + return ARM64_NGCS; + case ENC_NMATCH_P_P_ZZ_: + return ARM64_NMATCH; + case ENC_NOP_HI_HINTS: + return ARM64_NOP; + case ENC_NOR_P_P_PP_Z: + return ARM64_NOR; + case ENC_NORS_P_P_PP_Z: + return ARM64_NORS; + case ENC_NOT_ASIMDMISC_R: + case ENC_NOT_EOR_P_P_PP_Z: + case ENC_NOT_Z_P_Z_: + return ARM64_NOT; + case ENC_NOTS_EORS_P_P_PP_Z: + return ARM64_NOTS; + case ENC_ORN_ASIMDSAME_ONLY: + case ENC_ORN_32_LOG_SHIFT: + case ENC_ORN_64_LOG_SHIFT: + case ENC_ORN_ORR_Z_ZI_: + case ENC_ORN_P_P_PP_Z: + return ARM64_ORN; + case ENC_ORNS_P_P_PP_Z: + return ARM64_ORNS; + case ENC_ORR_ASIMDIMM_L_HL: + case ENC_ORR_ASIMDIMM_L_SL: + case ENC_ORR_ASIMDSAME_ONLY: + case ENC_ORR_32_LOG_IMM: + case ENC_ORR_64_LOG_IMM: + case ENC_ORR_32_LOG_SHIFT: + case ENC_ORR_64_LOG_SHIFT: + case ENC_ORR_P_P_PP_Z: + case ENC_ORR_Z_P_ZZ_: + case ENC_ORR_Z_ZI_: + case ENC_ORR_Z_ZZ_: + return ARM64_ORR; + case ENC_ORRS_P_P_PP_Z: + return ARM64_ORRS; + case ENC_ORV_R_P_Z_: + return ARM64_ORV; + case ENC_PACDA_64P_DP_1SRC: + return ARM64_PACDA; + case ENC_PACDB_64P_DP_1SRC: + return ARM64_PACDB; + case ENC_PACDZA_64Z_DP_1SRC: + return ARM64_PACDZA; + case ENC_PACDZB_64Z_DP_1SRC: + return ARM64_PACDZB; + case ENC_PACGA_64P_DP_2SRC: + return ARM64_PACGA; + case ENC_PACIA_64P_DP_1SRC: + return ARM64_PACIA; + case ENC_PACIA1716_HI_HINTS: + return ARM64_PACIA1716; + case ENC_PACIASP_HI_HINTS: + return ARM64_PACIASP; + case ENC_PACIAZ_HI_HINTS: + return ARM64_PACIAZ; + case ENC_PACIB_64P_DP_1SRC: + return ARM64_PACIB; + case ENC_PACIB1716_HI_HINTS: + return ARM64_PACIB1716; + case ENC_PACIBSP_HI_HINTS: + return ARM64_PACIBSP; + case ENC_PACIBZ_HI_HINTS: + return ARM64_PACIBZ; + case ENC_PACIZA_64Z_DP_1SRC: + return ARM64_PACIZA; + case ENC_PACIZB_64Z_DP_1SRC: + return ARM64_PACIZB; + case ENC_PFALSE_P_: + return ARM64_PFALSE; + case ENC_PFIRST_P_P_P_: + return ARM64_PFIRST; + case ENC_PMUL_ASIMDSAME_ONLY: + case ENC_PMUL_Z_ZZ_: + return ARM64_PMUL; + case ENC_PMULL_ASIMDDIFF_L: + return ARM64_PMULL; + //case ENC_PMULL_ASIMDDIFF_L: + // return ARM64_PMULL2; + case ENC_PMULLB_Z_ZZ_: + return ARM64_PMULLB; + case ENC_PMULLT_Z_ZZ_: + return ARM64_PMULLT; + case ENC_PNEXT_P_P_P_: + return ARM64_PNEXT; + case ENC_PRFB_I_P_AI_S: + case ENC_PRFB_I_P_AI_D: + case ENC_PRFB_I_P_BI_S: + case ENC_PRFB_I_P_BR_S: + case ENC_PRFB_I_P_BZ_S_X32_SCALED: + case ENC_PRFB_I_P_BZ_D_X32_SCALED: + case ENC_PRFB_I_P_BZ_D_64_SCALED: + return ARM64_PRFB; + case ENC_PRFD_I_P_AI_S: + case ENC_PRFD_I_P_AI_D: + case ENC_PRFD_I_P_BI_S: + case ENC_PRFD_I_P_BR_S: + case ENC_PRFD_I_P_BZ_S_X32_SCALED: + case ENC_PRFD_I_P_BZ_D_X32_SCALED: + case ENC_PRFD_I_P_BZ_D_64_SCALED: + return ARM64_PRFD; + case ENC_PRFH_I_P_AI_S: + case ENC_PRFH_I_P_AI_D: + case ENC_PRFH_I_P_BI_S: + case ENC_PRFH_I_P_BR_S: + case ENC_PRFH_I_P_BZ_S_X32_SCALED: + case ENC_PRFH_I_P_BZ_D_X32_SCALED: + case ENC_PRFH_I_P_BZ_D_64_SCALED: + return ARM64_PRFH; + case ENC_PRFM_P_LDST_POS: + case ENC_PRFM_P_LOADLIT: + case ENC_PRFM_P_LDST_REGOFF: + return ARM64_PRFM; + case ENC_PRFUM_P_LDST_UNSCALED: + return ARM64_PRFUM; + case ENC_PRFW_I_P_AI_S: + case ENC_PRFW_I_P_AI_D: + case ENC_PRFW_I_P_BI_S: + case ENC_PRFW_I_P_BR_S: + case ENC_PRFW_I_P_BZ_S_X32_SCALED: + case ENC_PRFW_I_P_BZ_D_X32_SCALED: + case ENC_PRFW_I_P_BZ_D_64_SCALED: + return ARM64_PRFW; + case ENC_PSB_HC_HINTS: + return ARM64_PSB; + case ENC_PSSBB_DSB_BO_BARRIERS: + return ARM64_PSSBB; + case ENC_PTEST_P_P_: + return ARM64_PTEST; + case ENC_PTRUE_P_S_: + return ARM64_PTRUE; + case ENC_PTRUES_P_S_: + return ARM64_PTRUES; + case ENC_PUNPKHI_P_P_: + return ARM64_PUNPKHI; + case ENC_PUNPKLO_P_P_: + return ARM64_PUNPKLO; + case ENC_RADDHN_ASIMDDIFF_N: + return ARM64_RADDHN; + //case ENC_RADDHN_ASIMDDIFF_N: + // return ARM64_RADDHN2; + case ENC_RADDHNB_Z_ZZ_: + return ARM64_RADDHNB; + case ENC_RADDHNT_Z_ZZ_: + return ARM64_RADDHNT; + case ENC_RAX1_VVV2_CRYPTOSHA512_3: + case ENC_RAX1_Z_ZZ_: + return ARM64_RAX1; + case ENC_RBIT_ASIMDMISC_R: + case ENC_RBIT_32_DP_1SRC: + case ENC_RBIT_64_DP_1SRC: + case ENC_RBIT_Z_P_Z_: + return ARM64_RBIT; + case ENC_RDFFR_P_F_: + case ENC_RDFFR_P_P_F_: + return ARM64_RDFFR; + case ENC_RDFFRS_P_P_F_: + return ARM64_RDFFRS; + case ENC_RDVL_R_I_: + return ARM64_RDVL; + case ENC_RET_64R_BRANCH_REG: + return ARM64_RET; + case ENC_RETAA_64E_BRANCH_REG: + return ARM64_RETAA; + case ENC_RETAB_64E_BRANCH_REG: + return ARM64_RETAB; + case ENC_REV_32_DP_1SRC: + case ENC_REV_64_DP_1SRC: + case ENC_REV_P_P_: + case ENC_REV_Z_Z_: + return ARM64_REV; + case ENC_REV16_ASIMDMISC_R: + case ENC_REV16_32_DP_1SRC: + case ENC_REV16_64_DP_1SRC: + return ARM64_REV16; + case ENC_REV32_ASIMDMISC_R: + case ENC_REV32_64_DP_1SRC: + return ARM64_REV32; + case ENC_REV64_REV_64_DP_1SRC: + case ENC_REV64_ASIMDMISC_R: + return ARM64_REV64; + case ENC_REVB_Z_Z_: + return ARM64_REVB; + case ENC_REVD_Z_P_Z_: + return ARM64_REVD; + case ENC_REVH_Z_Z_: + return ARM64_REVH; + case ENC_REVW_Z_Z_: + return ARM64_REVW; + case ENC_RMIF_ONLY_RMIF: + return ARM64_RMIF; + case ENC_ROR_EXTR_32_EXTRACT: + case ENC_ROR_EXTR_64_EXTRACT: + case ENC_ROR_RORV_32_DP_2SRC: + case ENC_ROR_RORV_64_DP_2SRC: + return ARM64_ROR; + case ENC_RORV_32_DP_2SRC: + case ENC_RORV_64_DP_2SRC: + return ARM64_RORV; + case ENC_RSHRN_ASIMDSHF_N: + return ARM64_RSHRN; + //case ENC_RSHRN_ASIMDSHF_N: + // return ARM64_RSHRN2; + case ENC_RSHRNB_Z_ZI_: + return ARM64_RSHRNB; + case ENC_RSHRNT_Z_ZI_: + return ARM64_RSHRNT; + case ENC_RSUBHN_ASIMDDIFF_N: + return ARM64_RSUBHN; + //case ENC_RSUBHN_ASIMDDIFF_N: + // return ARM64_RSUBHN2; + case ENC_RSUBHNB_Z_ZZ_: + return ARM64_RSUBHNB; + case ENC_RSUBHNT_Z_ZZ_: + return ARM64_RSUBHNT; + case ENC_SABA_ASIMDSAME_ONLY: + case ENC_SABA_Z_ZZZ_: + return ARM64_SABA; + case ENC_SABAL_ASIMDDIFF_L: + return ARM64_SABAL; + //case ENC_SABAL_ASIMDDIFF_L: + // return ARM64_SABAL2; + case ENC_SABALB_Z_ZZZ_: + return ARM64_SABALB; + case ENC_SABALT_Z_ZZZ_: + return ARM64_SABALT; + case ENC_SABD_ASIMDSAME_ONLY: + case ENC_SABD_Z_P_ZZ_: + return ARM64_SABD; + case ENC_SABDL_ASIMDDIFF_L: + return ARM64_SABDL; + //case ENC_SABDL_ASIMDDIFF_L: + // return ARM64_SABDL2; + case ENC_SABDLB_Z_ZZ_: + return ARM64_SABDLB; + case ENC_SABDLT_Z_ZZ_: + return ARM64_SABDLT; + case ENC_SADALP_ASIMDMISC_P: + case ENC_SADALP_Z_P_Z_: + return ARM64_SADALP; + case ENC_SADDL_ASIMDDIFF_L: + return ARM64_SADDL; + //case ENC_SADDL_ASIMDDIFF_L: + // return ARM64_SADDL2; + case ENC_SADDLB_Z_ZZ_: + return ARM64_SADDLB; + case ENC_SADDLBT_Z_ZZ_: + return ARM64_SADDLBT; + case ENC_SADDLP_ASIMDMISC_P: + return ARM64_SADDLP; + case ENC_SADDLT_Z_ZZ_: + return ARM64_SADDLT; + case ENC_SADDLV_ASIMDALL_ONLY: + return ARM64_SADDLV; + case ENC_SADDV_R_P_Z_: + return ARM64_SADDV; + case ENC_SADDW_ASIMDDIFF_W: + return ARM64_SADDW; + //case ENC_SADDW_ASIMDDIFF_W: + // return ARM64_SADDW2; + case ENC_SADDWB_Z_ZZ_: + return ARM64_SADDWB; + case ENC_SADDWT_Z_ZZ_: + return ARM64_SADDWT; + case ENC_SB_ONLY_BARRIERS: + return ARM64_SB; + case ENC_SBC_32_ADDSUB_CARRY: + case ENC_SBC_64_ADDSUB_CARRY: + return ARM64_SBC; + case ENC_SBCLB_Z_ZZZ_: + return ARM64_SBCLB; + case ENC_SBCLT_Z_ZZZ_: + return ARM64_SBCLT; + case ENC_SBCS_32_ADDSUB_CARRY: + case ENC_SBCS_64_ADDSUB_CARRY: + return ARM64_SBCS; + case ENC_SBFIZ_SBFM_32M_BITFIELD: + case ENC_SBFIZ_SBFM_64M_BITFIELD: + return ARM64_SBFIZ; + case ENC_SBFM_32M_BITFIELD: + case ENC_SBFM_64M_BITFIELD: + return ARM64_SBFM; + case ENC_SBFX_SBFM_32M_BITFIELD: + case ENC_SBFX_SBFM_64M_BITFIELD: + return ARM64_SBFX; + case ENC_SCLAMP_Z_ZZ_: + return ARM64_SCLAMP; + case ENC_SCVTF_ASISDSHF_C: + case ENC_SCVTF_ASIMDSHF_C: + case ENC_SCVTF_ASISDMISCFP16_R: + case ENC_SCVTF_ASISDMISC_R: + case ENC_SCVTF_ASIMDMISCFP16_R: + case ENC_SCVTF_ASIMDMISC_R: + case ENC_SCVTF_H32_FLOAT2FIX: + case ENC_SCVTF_S32_FLOAT2FIX: + case ENC_SCVTF_D32_FLOAT2FIX: + case ENC_SCVTF_H64_FLOAT2FIX: + case ENC_SCVTF_S64_FLOAT2FIX: + case ENC_SCVTF_D64_FLOAT2FIX: + case ENC_SCVTF_H32_FLOAT2INT: + case ENC_SCVTF_S32_FLOAT2INT: + case ENC_SCVTF_D32_FLOAT2INT: + case ENC_SCVTF_H64_FLOAT2INT: + case ENC_SCVTF_S64_FLOAT2INT: + case ENC_SCVTF_D64_FLOAT2INT: + case ENC_SCVTF_Z_P_Z_H2FP16: + case ENC_SCVTF_Z_P_Z_W2FP16: + case ENC_SCVTF_Z_P_Z_W2S: + case ENC_SCVTF_Z_P_Z_W2D: + case ENC_SCVTF_Z_P_Z_X2FP16: + case ENC_SCVTF_Z_P_Z_X2S: + case ENC_SCVTF_Z_P_Z_X2D: + return ARM64_SCVTF; + case ENC_SDIV_32_DP_2SRC: + case ENC_SDIV_64_DP_2SRC: + case ENC_SDIV_Z_P_ZZ_: + return ARM64_SDIV; + case ENC_SDIVR_Z_P_ZZ_: + return ARM64_SDIVR; + case ENC_SDOT_ASIMDELEM_D: + case ENC_SDOT_ASIMDSAME2_D: + case ENC_SDOT_Z_ZZZ_: + case ENC_SDOT_Z_ZZZI_S: + case ENC_SDOT_Z_ZZZI_D: + return ARM64_SDOT; + case ENC_SEL_P_P_PP_: + case ENC_SEL_Z_P_ZZ_: + return ARM64_SEL; + case ENC_SETF16_ONLY_SETF: + return ARM64_SETF16; + case ENC_SETF8_ONLY_SETF: + return ARM64_SETF8; + case ENC_SETFFR_F_: + return ARM64_SETFFR; + case ENC_SEV_HI_HINTS: + return ARM64_SEV; + case ENC_SEVL_HI_HINTS: + return ARM64_SEVL; + case ENC_SHA1C_QSV_CRYPTOSHA3: + return ARM64_SHA1C; + case ENC_SHA1H_SS_CRYPTOSHA2: + return ARM64_SHA1H; + case ENC_SHA1M_QSV_CRYPTOSHA3: + return ARM64_SHA1M; + case ENC_SHA1P_QSV_CRYPTOSHA3: + return ARM64_SHA1P; + case ENC_SHA1SU0_VVV_CRYPTOSHA3: + return ARM64_SHA1SU0; + case ENC_SHA1SU1_VV_CRYPTOSHA2: + return ARM64_SHA1SU1; + case ENC_SHA256H_QQV_CRYPTOSHA3: + return ARM64_SHA256H; + case ENC_SHA256H2_QQV_CRYPTOSHA3: + return ARM64_SHA256H2; + case ENC_SHA256SU0_VV_CRYPTOSHA2: + return ARM64_SHA256SU0; + case ENC_SHA256SU1_VVV_CRYPTOSHA3: + return ARM64_SHA256SU1; + case ENC_SHA512H_QQV_CRYPTOSHA512_3: + return ARM64_SHA512H; + case ENC_SHA512H2_QQV_CRYPTOSHA512_3: + return ARM64_SHA512H2; + case ENC_SHA512SU0_VV2_CRYPTOSHA512_2: + return ARM64_SHA512SU0; + case ENC_SHA512SU1_VVV2_CRYPTOSHA512_3: + return ARM64_SHA512SU1; + case ENC_SHADD_ASIMDSAME_ONLY: + case ENC_SHADD_Z_P_ZZ_: + return ARM64_SHADD; + case ENC_SHL_ASISDSHF_R: + case ENC_SHL_ASIMDSHF_R: + return ARM64_SHL; + case ENC_SHLL_ASIMDMISC_S: + return ARM64_SHLL; + //case ENC_SHLL_ASIMDMISC_S: + // return ARM64_SHLL2; + case ENC_SHRN_ASIMDSHF_N: + return ARM64_SHRN; + //case ENC_SHRN_ASIMDSHF_N: + // return ARM64_SHRN2; + case ENC_SHRNB_Z_ZI_: + return ARM64_SHRNB; + case ENC_SHRNT_Z_ZI_: + return ARM64_SHRNT; + case ENC_SHSUB_ASIMDSAME_ONLY: + case ENC_SHSUB_Z_P_ZZ_: + return ARM64_SHSUB; + case ENC_SHSUBR_Z_P_ZZ_: + return ARM64_SHSUBR; + case ENC_SLI_ASISDSHF_R: + case ENC_SLI_ASIMDSHF_R: + case ENC_SLI_Z_ZZI_: + return ARM64_SLI; + case ENC_SM3PARTW1_VVV4_CRYPTOSHA512_3: + return ARM64_SM3PARTW1; + case ENC_SM3PARTW2_VVV4_CRYPTOSHA512_3: + return ARM64_SM3PARTW2; + case ENC_SM3SS1_VVV4_CRYPTO4: + return ARM64_SM3SS1; + case ENC_SM3TT1A_VVV4_CRYPTO3_IMM2: + return ARM64_SM3TT1A; + case ENC_SM3TT1B_VVV4_CRYPTO3_IMM2: + return ARM64_SM3TT1B; + case ENC_SM3TT2A_VVV4_CRYPTO3_IMM2: + return ARM64_SM3TT2A; + case ENC_SM3TT2B_VVV_CRYPTO3_IMM2: + return ARM64_SM3TT2B; + case ENC_SM4E_VV4_CRYPTOSHA512_2: + case ENC_SM4E_Z_ZZ_: + return ARM64_SM4E; + case ENC_SM4EKEY_VVV4_CRYPTOSHA512_3: + case ENC_SM4EKEY_Z_ZZ_: + return ARM64_SM4EKEY; + case ENC_SMADDL_64WA_DP_3SRC: + return ARM64_SMADDL; + case ENC_SMAX_ASIMDSAME_ONLY: + case ENC_SMAX_Z_P_ZZ_: + case ENC_SMAX_Z_ZI_: + return ARM64_SMAX; + case ENC_SMAXP_ASIMDSAME_ONLY: + case ENC_SMAXP_Z_P_ZZ_: + return ARM64_SMAXP; + case ENC_SMAXV_ASIMDALL_ONLY: + case ENC_SMAXV_R_P_Z_: + return ARM64_SMAXV; + case ENC_SMC_EX_EXCEPTION: + return ARM64_SMC; + case ENC_SMIN_ASIMDSAME_ONLY: + case ENC_SMIN_Z_P_ZZ_: + case ENC_SMIN_Z_ZI_: + return ARM64_SMIN; + case ENC_SMINP_ASIMDSAME_ONLY: + case ENC_SMINP_Z_P_ZZ_: + return ARM64_SMINP; + case ENC_SMINV_ASIMDALL_ONLY: + case ENC_SMINV_R_P_Z_: + return ARM64_SMINV; + case ENC_SMLAL_ASIMDELEM_L: + case ENC_SMLAL_ASIMDDIFF_L: + return ARM64_SMLAL; + //case ENC_SMLAL_ASIMDELEM_L: + //case ENC_SMLAL_ASIMDDIFF_L: + // return ARM64_SMLAL2; + case ENC_SMLALB_Z_ZZZ_: + case ENC_SMLALB_Z_ZZZI_S: + case ENC_SMLALB_Z_ZZZI_D: + return ARM64_SMLALB; + case ENC_SMLALT_Z_ZZZ_: + case ENC_SMLALT_Z_ZZZI_S: + case ENC_SMLALT_Z_ZZZI_D: + return ARM64_SMLALT; + case ENC_SMLSL_ASIMDELEM_L: + case ENC_SMLSL_ASIMDDIFF_L: + return ARM64_SMLSL; + //case ENC_SMLSL_ASIMDELEM_L: + //case ENC_SMLSL_ASIMDDIFF_L: + // return ARM64_SMLSL2; + case ENC_SMLSLB_Z_ZZZ_: + case ENC_SMLSLB_Z_ZZZI_S: + case ENC_SMLSLB_Z_ZZZI_D: + return ARM64_SMLSLB; + case ENC_SMLSLT_Z_ZZZ_: + case ENC_SMLSLT_Z_ZZZI_S: + case ENC_SMLSLT_Z_ZZZI_D: + return ARM64_SMLSLT; + case ENC_SMMLA_ASIMDSAME2_G: + case ENC_SMMLA_Z_ZZZ_: + return ARM64_SMMLA; + case ENC_SMNEGL_SMSUBL_64WA_DP_3SRC: + return ARM64_SMNEGL; + case ENC_SMOPA_ZA_PP_ZZ_32: + case ENC_SMOPA_ZA_PP_ZZ_64: + return ARM64_SMOPA; + case ENC_SMOPS_ZA_PP_ZZ_32: + case ENC_SMOPS_ZA_PP_ZZ_64: + return ARM64_SMOPS; + case ENC_SMOV_ASIMDINS_W_W: + case ENC_SMOV_ASIMDINS_X_X: + return ARM64_SMOV; + case ENC_SMSTART_MSR_SI_PSTATE: + return ARM64_SMSTART; + case ENC_SMSTOP_MSR_SI_PSTATE: + return ARM64_SMSTOP; + case ENC_SMSUBL_64WA_DP_3SRC: + return ARM64_SMSUBL; + case ENC_SMULH_64_DP_3SRC: + case ENC_SMULH_Z_P_ZZ_: + case ENC_SMULH_Z_ZZ_: + return ARM64_SMULH; + case ENC_SMULL_SMADDL_64WA_DP_3SRC: + case ENC_SMULL_ASIMDELEM_L: + case ENC_SMULL_ASIMDDIFF_L: + return ARM64_SMULL; + //case ENC_SMULL_ASIMDELEM_L: + //case ENC_SMULL_ASIMDDIFF_L: + // return ARM64_SMULL2; + case ENC_SMULLB_Z_ZZ_: + case ENC_SMULLB_Z_ZZI_S: + case ENC_SMULLB_Z_ZZI_D: + return ARM64_SMULLB; + case ENC_SMULLT_Z_ZZ_: + case ENC_SMULLT_Z_ZZI_S: + case ENC_SMULLT_Z_ZZI_D: + return ARM64_SMULLT; + case ENC_SPLICE_Z_P_ZZ_CON: + case ENC_SPLICE_Z_P_ZZ_DES: + return ARM64_SPLICE; + case ENC_SQABS_ASISDMISC_R: + case ENC_SQABS_ASIMDMISC_R: + case ENC_SQABS_Z_P_Z_: + return ARM64_SQABS; + case ENC_SQADD_ASISDSAME_ONLY: + case ENC_SQADD_ASIMDSAME_ONLY: + case ENC_SQADD_Z_P_ZZ_: + case ENC_SQADD_Z_ZI_: + case ENC_SQADD_Z_ZZ_: + return ARM64_SQADD; + case ENC_SQCADD_Z_ZZ_: + return ARM64_SQCADD; + case ENC_SQDECB_R_RS_SX: + case ENC_SQDECB_R_RS_X: + return ARM64_SQDECB; + case ENC_SQDECD_R_RS_SX: + case ENC_SQDECD_R_RS_X: + case ENC_SQDECD_Z_ZS_: + return ARM64_SQDECD; + case ENC_SQDECH_R_RS_SX: + case ENC_SQDECH_R_RS_X: + case ENC_SQDECH_Z_ZS_: + return ARM64_SQDECH; + case ENC_SQDECP_R_P_R_SX: + case ENC_SQDECP_R_P_R_X: + case ENC_SQDECP_Z_P_Z_: + return ARM64_SQDECP; + case ENC_SQDECW_R_RS_SX: + case ENC_SQDECW_R_RS_X: + case ENC_SQDECW_Z_ZS_: + return ARM64_SQDECW; + case ENC_SQDMLAL_ASISDELEM_L: + case ENC_SQDMLAL_ASIMDELEM_L: + case ENC_SQDMLAL_ASISDDIFF_ONLY: + case ENC_SQDMLAL_ASIMDDIFF_L: + return ARM64_SQDMLAL; + //case ENC_SQDMLAL_ASIMDELEM_L: + //case ENC_SQDMLAL_ASIMDDIFF_L: + // return ARM64_SQDMLAL2; + case ENC_SQDMLALB_Z_ZZZ_: + case ENC_SQDMLALB_Z_ZZZI_S: + case ENC_SQDMLALB_Z_ZZZI_D: + return ARM64_SQDMLALB; + case ENC_SQDMLALBT_Z_ZZZ_: + return ARM64_SQDMLALBT; + case ENC_SQDMLALT_Z_ZZZ_: + case ENC_SQDMLALT_Z_ZZZI_S: + case ENC_SQDMLALT_Z_ZZZI_D: + return ARM64_SQDMLALT; + case ENC_SQDMLSL_ASISDELEM_L: + case ENC_SQDMLSL_ASIMDELEM_L: + case ENC_SQDMLSL_ASISDDIFF_ONLY: + case ENC_SQDMLSL_ASIMDDIFF_L: + return ARM64_SQDMLSL; + //case ENC_SQDMLSL_ASIMDELEM_L: + //case ENC_SQDMLSL_ASIMDDIFF_L: + // return ARM64_SQDMLSL2; + case ENC_SQDMLSLB_Z_ZZZ_: + case ENC_SQDMLSLB_Z_ZZZI_S: + case ENC_SQDMLSLB_Z_ZZZI_D: + return ARM64_SQDMLSLB; + case ENC_SQDMLSLBT_Z_ZZZ_: + return ARM64_SQDMLSLBT; + case ENC_SQDMLSLT_Z_ZZZ_: + case ENC_SQDMLSLT_Z_ZZZI_S: + case ENC_SQDMLSLT_Z_ZZZI_D: + return ARM64_SQDMLSLT; + case ENC_SQDMULH_ASISDELEM_R: + case ENC_SQDMULH_ASIMDELEM_R: + case ENC_SQDMULH_ASISDSAME_ONLY: + case ENC_SQDMULH_ASIMDSAME_ONLY: + case ENC_SQDMULH_Z_ZZ_: + case ENC_SQDMULH_Z_ZZI_H: + case ENC_SQDMULH_Z_ZZI_S: + case ENC_SQDMULH_Z_ZZI_D: + return ARM64_SQDMULH; + case ENC_SQDMULL_ASISDELEM_L: + case ENC_SQDMULL_ASIMDELEM_L: + case ENC_SQDMULL_ASISDDIFF_ONLY: + case ENC_SQDMULL_ASIMDDIFF_L: + return ARM64_SQDMULL; + //case ENC_SQDMULL_ASIMDELEM_L: + //case ENC_SQDMULL_ASIMDDIFF_L: + // return ARM64_SQDMULL2; + case ENC_SQDMULLB_Z_ZZ_: + case ENC_SQDMULLB_Z_ZZI_S: + case ENC_SQDMULLB_Z_ZZI_D: + return ARM64_SQDMULLB; + case ENC_SQDMULLT_Z_ZZ_: + case ENC_SQDMULLT_Z_ZZI_S: + case ENC_SQDMULLT_Z_ZZI_D: + return ARM64_SQDMULLT; + case ENC_SQINCB_R_RS_SX: + case ENC_SQINCB_R_RS_X: + return ARM64_SQINCB; + case ENC_SQINCD_R_RS_SX: + case ENC_SQINCD_R_RS_X: + case ENC_SQINCD_Z_ZS_: + return ARM64_SQINCD; + case ENC_SQINCH_R_RS_SX: + case ENC_SQINCH_R_RS_X: + case ENC_SQINCH_Z_ZS_: + return ARM64_SQINCH; + case ENC_SQINCP_R_P_R_SX: + case ENC_SQINCP_R_P_R_X: + case ENC_SQINCP_Z_P_Z_: + return ARM64_SQINCP; + case ENC_SQINCW_R_RS_SX: + case ENC_SQINCW_R_RS_X: + case ENC_SQINCW_Z_ZS_: + return ARM64_SQINCW; + case ENC_SQNEG_ASISDMISC_R: + case ENC_SQNEG_ASIMDMISC_R: + case ENC_SQNEG_Z_P_Z_: + return ARM64_SQNEG; + case ENC_SQRDCMLAH_Z_ZZZ_: + case ENC_SQRDCMLAH_Z_ZZZI_H: + case ENC_SQRDCMLAH_Z_ZZZI_S: + return ARM64_SQRDCMLAH; + case ENC_SQRDMLAH_ASISDELEM_R: + case ENC_SQRDMLAH_ASIMDELEM_R: + case ENC_SQRDMLAH_ASISDSAME2_ONLY: + case ENC_SQRDMLAH_ASIMDSAME2_ONLY: + case ENC_SQRDMLAH_Z_ZZZ_: + case ENC_SQRDMLAH_Z_ZZZI_H: + case ENC_SQRDMLAH_Z_ZZZI_S: + case ENC_SQRDMLAH_Z_ZZZI_D: + return ARM64_SQRDMLAH; + case ENC_SQRDMLSH_ASISDELEM_R: + case ENC_SQRDMLSH_ASIMDELEM_R: + case ENC_SQRDMLSH_ASISDSAME2_ONLY: + case ENC_SQRDMLSH_ASIMDSAME2_ONLY: + case ENC_SQRDMLSH_Z_ZZZ_: + case ENC_SQRDMLSH_Z_ZZZI_H: + case ENC_SQRDMLSH_Z_ZZZI_S: + case ENC_SQRDMLSH_Z_ZZZI_D: + return ARM64_SQRDMLSH; + case ENC_SQRDMULH_ASISDELEM_R: + case ENC_SQRDMULH_ASIMDELEM_R: + case ENC_SQRDMULH_ASISDSAME_ONLY: + case ENC_SQRDMULH_ASIMDSAME_ONLY: + case ENC_SQRDMULH_Z_ZZ_: + case ENC_SQRDMULH_Z_ZZI_H: + case ENC_SQRDMULH_Z_ZZI_S: + case ENC_SQRDMULH_Z_ZZI_D: + return ARM64_SQRDMULH; + case ENC_SQRSHL_ASISDSAME_ONLY: + case ENC_SQRSHL_ASIMDSAME_ONLY: + case ENC_SQRSHL_Z_P_ZZ_: + return ARM64_SQRSHL; + case ENC_SQRSHLR_Z_P_ZZ_: + return ARM64_SQRSHLR; + case ENC_SQRSHRN_ASISDSHF_N: + case ENC_SQRSHRN_ASIMDSHF_N: + return ARM64_SQRSHRN; + //case ENC_SQRSHRN_ASIMDSHF_N: + // return ARM64_SQRSHRN2; + case ENC_SQRSHRNB_Z_ZI_: + return ARM64_SQRSHRNB; + case ENC_SQRSHRNT_Z_ZI_: + return ARM64_SQRSHRNT; + case ENC_SQRSHRUN_ASISDSHF_N: + case ENC_SQRSHRUN_ASIMDSHF_N: + return ARM64_SQRSHRUN; + //case ENC_SQRSHRUN_ASIMDSHF_N: + // return ARM64_SQRSHRUN2; + case ENC_SQRSHRUNB_Z_ZI_: + return ARM64_SQRSHRUNB; + case ENC_SQRSHRUNT_Z_ZI_: + return ARM64_SQRSHRUNT; + case ENC_SQSHL_ASISDSHF_R: + case ENC_SQSHL_ASIMDSHF_R: + case ENC_SQSHL_ASISDSAME_ONLY: + case ENC_SQSHL_ASIMDSAME_ONLY: + case ENC_SQSHL_Z_P_ZI_: + case ENC_SQSHL_Z_P_ZZ_: + return ARM64_SQSHL; + case ENC_SQSHLR_Z_P_ZZ_: + return ARM64_SQSHLR; + case ENC_SQSHLU_ASISDSHF_R: + case ENC_SQSHLU_ASIMDSHF_R: + case ENC_SQSHLU_Z_P_ZI_: + return ARM64_SQSHLU; + case ENC_SQSHRN_ASISDSHF_N: + case ENC_SQSHRN_ASIMDSHF_N: + return ARM64_SQSHRN; + //case ENC_SQSHRN_ASIMDSHF_N: + // return ARM64_SQSHRN2; + case ENC_SQSHRNB_Z_ZI_: + return ARM64_SQSHRNB; + case ENC_SQSHRNT_Z_ZI_: + return ARM64_SQSHRNT; + case ENC_SQSHRUN_ASISDSHF_N: + case ENC_SQSHRUN_ASIMDSHF_N: + return ARM64_SQSHRUN; + //case ENC_SQSHRUN_ASIMDSHF_N: + // return ARM64_SQSHRUN2; + case ENC_SQSHRUNB_Z_ZI_: + return ARM64_SQSHRUNB; + case ENC_SQSHRUNT_Z_ZI_: + return ARM64_SQSHRUNT; + case ENC_SQSUB_ASISDSAME_ONLY: + case ENC_SQSUB_ASIMDSAME_ONLY: + case ENC_SQSUB_Z_P_ZZ_: + case ENC_SQSUB_Z_ZI_: + case ENC_SQSUB_Z_ZZ_: + return ARM64_SQSUB; + case ENC_SQSUBR_Z_P_ZZ_: + return ARM64_SQSUBR; + case ENC_SQXTN_ASISDMISC_N: + case ENC_SQXTN_ASIMDMISC_N: + return ARM64_SQXTN; + //case ENC_SQXTN_ASIMDMISC_N: + // return ARM64_SQXTN2; + case ENC_SQXTNB_Z_ZZ_: + return ARM64_SQXTNB; + case ENC_SQXTNT_Z_ZZ_: + return ARM64_SQXTNT; + case ENC_SQXTUN_ASISDMISC_N: + case ENC_SQXTUN_ASIMDMISC_N: + return ARM64_SQXTUN; + //case ENC_SQXTUN_ASIMDMISC_N: + // return ARM64_SQXTUN2; + case ENC_SQXTUNB_Z_ZZ_: + return ARM64_SQXTUNB; + case ENC_SQXTUNT_Z_ZZ_: + return ARM64_SQXTUNT; + case ENC_SRHADD_ASIMDSAME_ONLY: + case ENC_SRHADD_Z_P_ZZ_: + return ARM64_SRHADD; + case ENC_SRI_ASISDSHF_R: + case ENC_SRI_ASIMDSHF_R: + case ENC_SRI_Z_ZZI_: + return ARM64_SRI; + case ENC_SRSHL_ASISDSAME_ONLY: + case ENC_SRSHL_ASIMDSAME_ONLY: + case ENC_SRSHL_Z_P_ZZ_: + return ARM64_SRSHL; + case ENC_SRSHLR_Z_P_ZZ_: + return ARM64_SRSHLR; + case ENC_SRSHR_ASISDSHF_R: + case ENC_SRSHR_ASIMDSHF_R: + case ENC_SRSHR_Z_P_ZI_: + return ARM64_SRSHR; + case ENC_SRSRA_ASISDSHF_R: + case ENC_SRSRA_ASIMDSHF_R: + case ENC_SRSRA_Z_ZI_: + return ARM64_SRSRA; + case ENC_SSBB_DSB_BO_BARRIERS: + return ARM64_SSBB; + case ENC_SSHL_ASISDSAME_ONLY: + case ENC_SSHL_ASIMDSAME_ONLY: + return ARM64_SSHL; + case ENC_SSHLL_ASIMDSHF_L: + return ARM64_SSHLL; + //case ENC_SSHLL_ASIMDSHF_L: + // return ARM64_SSHLL2; + case ENC_SSHLLB_Z_ZI_: + return ARM64_SSHLLB; + case ENC_SSHLLT_Z_ZI_: + return ARM64_SSHLLT; + case ENC_SSHR_ASISDSHF_R: + case ENC_SSHR_ASIMDSHF_R: + return ARM64_SSHR; + case ENC_SSRA_ASISDSHF_R: + case ENC_SSRA_ASIMDSHF_R: + case ENC_SSRA_Z_ZI_: + return ARM64_SSRA; + case ENC_SSUBL_ASIMDDIFF_L: + return ARM64_SSUBL; + //case ENC_SSUBL_ASIMDDIFF_L: + // return ARM64_SSUBL2; + case ENC_SSUBLB_Z_ZZ_: + return ARM64_SSUBLB; + case ENC_SSUBLBT_Z_ZZ_: + return ARM64_SSUBLBT; + case ENC_SSUBLT_Z_ZZ_: + return ARM64_SSUBLT; + case ENC_SSUBLTB_Z_ZZ_: + return ARM64_SSUBLTB; + case ENC_SSUBW_ASIMDDIFF_W: + return ARM64_SSUBW; + //case ENC_SSUBW_ASIMDDIFF_W: + // return ARM64_SSUBW2; + case ENC_SSUBWB_Z_ZZ_: + return ARM64_SSUBWB; + case ENC_SSUBWT_Z_ZZ_: + return ARM64_SSUBWT; + case ENC_ST1_ASISDLSE_R1_1V: + case ENC_ST1_ASISDLSE_R2_2V: + case ENC_ST1_ASISDLSE_R3_3V: + case ENC_ST1_ASISDLSE_R4_4V: + case ENC_ST1_ASISDLSEP_I1_I1: + case ENC_ST1_ASISDLSEP_R1_R1: + case ENC_ST1_ASISDLSEP_I2_I2: + case ENC_ST1_ASISDLSEP_R2_R2: + case ENC_ST1_ASISDLSEP_I3_I3: + case ENC_ST1_ASISDLSEP_R3_R3: + case ENC_ST1_ASISDLSEP_I4_I4: + case ENC_ST1_ASISDLSEP_R4_R4: + case ENC_ST1_ASISDLSO_B1_1B: + case ENC_ST1_ASISDLSO_H1_1H: + case ENC_ST1_ASISDLSO_S1_1S: + case ENC_ST1_ASISDLSO_D1_1D: + case ENC_ST1_ASISDLSOP_B1_I1B: + case ENC_ST1_ASISDLSOP_BX1_R1B: + case ENC_ST1_ASISDLSOP_H1_I1H: + case ENC_ST1_ASISDLSOP_HX1_R1H: + case ENC_ST1_ASISDLSOP_S1_I1S: + case ENC_ST1_ASISDLSOP_SX1_R1S: + case ENC_ST1_ASISDLSOP_D1_I1D: + case ENC_ST1_ASISDLSOP_DX1_R1D: + return ARM64_ST1; + case ENC_ST1B_Z_P_AI_S: + case ENC_ST1B_Z_P_AI_D: + case ENC_ST1B_Z_P_BI_: + case ENC_ST1B_Z_P_BR_: + case ENC_ST1B_Z_P_BZ_D_X32_UNSCALED: + case ENC_ST1B_Z_P_BZ_S_X32_UNSCALED: + case ENC_ST1B_Z_P_BZ_D_64_UNSCALED: + case ENC_ST1B_ZA_P_RRR_: + return ARM64_ST1B; + case ENC_ST1D_Z_P_AI_D: + case ENC_ST1D_Z_P_BI_: + case ENC_ST1D_Z_P_BR_: + case ENC_ST1D_Z_P_BZ_D_X32_SCALED: + case ENC_ST1D_Z_P_BZ_D_X32_UNSCALED: + case ENC_ST1D_Z_P_BZ_D_64_SCALED: + case ENC_ST1D_Z_P_BZ_D_64_UNSCALED: + case ENC_ST1D_ZA_P_RRR_: + return ARM64_ST1D; + case ENC_ST1H_Z_P_AI_S: + case ENC_ST1H_Z_P_AI_D: + case ENC_ST1H_Z_P_BI_: + case ENC_ST1H_Z_P_BR_: + case ENC_ST1H_Z_P_BZ_S_X32_SCALED: + case ENC_ST1H_Z_P_BZ_D_X32_SCALED: + case ENC_ST1H_Z_P_BZ_D_X32_UNSCALED: + case ENC_ST1H_Z_P_BZ_S_X32_UNSCALED: + case ENC_ST1H_Z_P_BZ_D_64_SCALED: + case ENC_ST1H_Z_P_BZ_D_64_UNSCALED: + case ENC_ST1H_ZA_P_RRR_: + return ARM64_ST1H; + case ENC_ST1Q_ZA_P_RRR_: + return ARM64_ST1Q; + case ENC_ST1W_Z_P_AI_S: + case ENC_ST1W_Z_P_AI_D: + case ENC_ST1W_Z_P_BI_: + case ENC_ST1W_Z_P_BR_: + case ENC_ST1W_Z_P_BZ_S_X32_SCALED: + case ENC_ST1W_Z_P_BZ_D_X32_SCALED: + case ENC_ST1W_Z_P_BZ_D_X32_UNSCALED: + case ENC_ST1W_Z_P_BZ_S_X32_UNSCALED: + case ENC_ST1W_Z_P_BZ_D_64_SCALED: + case ENC_ST1W_Z_P_BZ_D_64_UNSCALED: + case ENC_ST1W_ZA_P_RRR_: + return ARM64_ST1W; + case ENC_ST2_ASISDLSE_R2: + case ENC_ST2_ASISDLSEP_I2_I: + case ENC_ST2_ASISDLSEP_R2_R: + case ENC_ST2_ASISDLSO_B2_2B: + case ENC_ST2_ASISDLSO_H2_2H: + case ENC_ST2_ASISDLSO_S2_2S: + case ENC_ST2_ASISDLSO_D2_2D: + case ENC_ST2_ASISDLSOP_B2_I2B: + case ENC_ST2_ASISDLSOP_BX2_R2B: + case ENC_ST2_ASISDLSOP_H2_I2H: + case ENC_ST2_ASISDLSOP_HX2_R2H: + case ENC_ST2_ASISDLSOP_S2_I2S: + case ENC_ST2_ASISDLSOP_SX2_R2S: + case ENC_ST2_ASISDLSOP_D2_I2D: + case ENC_ST2_ASISDLSOP_DX2_R2D: + return ARM64_ST2; + case ENC_ST2B_Z_P_BI_CONTIGUOUS: + case ENC_ST2B_Z_P_BR_CONTIGUOUS: + return ARM64_ST2B; + case ENC_ST2D_Z_P_BI_CONTIGUOUS: + case ENC_ST2D_Z_P_BR_CONTIGUOUS: + return ARM64_ST2D; + case ENC_ST2G_64SPOST_LDSTTAGS: + case ENC_ST2G_64SPRE_LDSTTAGS: + case ENC_ST2G_64SOFFSET_LDSTTAGS: + return ARM64_ST2G; + case ENC_ST2H_Z_P_BI_CONTIGUOUS: + case ENC_ST2H_Z_P_BR_CONTIGUOUS: + return ARM64_ST2H; + case ENC_ST2W_Z_P_BI_CONTIGUOUS: + case ENC_ST2W_Z_P_BR_CONTIGUOUS: + return ARM64_ST2W; + case ENC_ST3_ASISDLSE_R3: + case ENC_ST3_ASISDLSEP_I3_I: + case ENC_ST3_ASISDLSEP_R3_R: + case ENC_ST3_ASISDLSO_B3_3B: + case ENC_ST3_ASISDLSO_H3_3H: + case ENC_ST3_ASISDLSO_S3_3S: + case ENC_ST3_ASISDLSO_D3_3D: + case ENC_ST3_ASISDLSOP_B3_I3B: + case ENC_ST3_ASISDLSOP_BX3_R3B: + case ENC_ST3_ASISDLSOP_H3_I3H: + case ENC_ST3_ASISDLSOP_HX3_R3H: + case ENC_ST3_ASISDLSOP_S3_I3S: + case ENC_ST3_ASISDLSOP_SX3_R3S: + case ENC_ST3_ASISDLSOP_D3_I3D: + case ENC_ST3_ASISDLSOP_DX3_R3D: + return ARM64_ST3; + case ENC_ST3B_Z_P_BI_CONTIGUOUS: + case ENC_ST3B_Z_P_BR_CONTIGUOUS: + return ARM64_ST3B; + case ENC_ST3D_Z_P_BI_CONTIGUOUS: + case ENC_ST3D_Z_P_BR_CONTIGUOUS: + return ARM64_ST3D; + case ENC_ST3H_Z_P_BI_CONTIGUOUS: + case ENC_ST3H_Z_P_BR_CONTIGUOUS: + return ARM64_ST3H; + case ENC_ST3W_Z_P_BI_CONTIGUOUS: + case ENC_ST3W_Z_P_BR_CONTIGUOUS: + return ARM64_ST3W; + case ENC_ST4_ASISDLSE_R4: + case ENC_ST4_ASISDLSEP_I4_I: + case ENC_ST4_ASISDLSEP_R4_R: + case ENC_ST4_ASISDLSO_B4_4B: + case ENC_ST4_ASISDLSO_H4_4H: + case ENC_ST4_ASISDLSO_S4_4S: + case ENC_ST4_ASISDLSO_D4_4D: + case ENC_ST4_ASISDLSOP_B4_I4B: + case ENC_ST4_ASISDLSOP_BX4_R4B: + case ENC_ST4_ASISDLSOP_H4_I4H: + case ENC_ST4_ASISDLSOP_HX4_R4H: + case ENC_ST4_ASISDLSOP_S4_I4S: + case ENC_ST4_ASISDLSOP_SX4_R4S: + case ENC_ST4_ASISDLSOP_D4_I4D: + case ENC_ST4_ASISDLSOP_DX4_R4D: + return ARM64_ST4; + case ENC_ST4B_Z_P_BI_CONTIGUOUS: + case ENC_ST4B_Z_P_BR_CONTIGUOUS: + return ARM64_ST4B; + case ENC_ST4D_Z_P_BI_CONTIGUOUS: + case ENC_ST4D_Z_P_BR_CONTIGUOUS: + return ARM64_ST4D; + case ENC_ST4H_Z_P_BI_CONTIGUOUS: + case ENC_ST4H_Z_P_BR_CONTIGUOUS: + return ARM64_ST4H; + case ENC_ST4W_Z_P_BI_CONTIGUOUS: + case ENC_ST4W_Z_P_BR_CONTIGUOUS: + return ARM64_ST4W; + case ENC_ST64B_64L_MEMOP: + return ARM64_ST64B; + case ENC_ST64BV_64_MEMOP: + return ARM64_ST64BV; + case ENC_ST64BV0_64_MEMOP: + return ARM64_ST64BV0; + case ENC_STADD_LDADD_32_MEMOP: + case ENC_STADD_LDADD_64_MEMOP: + return ARM64_STADD; + case ENC_STADDB_LDADDB_32_MEMOP: + return ARM64_STADDB; + case ENC_STADDH_LDADDH_32_MEMOP: + return ARM64_STADDH; + case ENC_STADDL_LDADDL_32_MEMOP: + case ENC_STADDL_LDADDL_64_MEMOP: + return ARM64_STADDL; + case ENC_STADDLB_LDADDLB_32_MEMOP: + return ARM64_STADDLB; + case ENC_STADDLH_LDADDLH_32_MEMOP: + return ARM64_STADDLH; + case ENC_STCLR_LDCLR_32_MEMOP: + case ENC_STCLR_LDCLR_64_MEMOP: + return ARM64_STCLR; + case ENC_STCLRB_LDCLRB_32_MEMOP: + return ARM64_STCLRB; + case ENC_STCLRH_LDCLRH_32_MEMOP: + return ARM64_STCLRH; + case ENC_STCLRL_LDCLRL_32_MEMOP: + case ENC_STCLRL_LDCLRL_64_MEMOP: + return ARM64_STCLRL; + case ENC_STCLRLB_LDCLRLB_32_MEMOP: + return ARM64_STCLRLB; + case ENC_STCLRLH_LDCLRLH_32_MEMOP: + return ARM64_STCLRLH; + case ENC_STEOR_LDEOR_32_MEMOP: + case ENC_STEOR_LDEOR_64_MEMOP: + return ARM64_STEOR; + case ENC_STEORB_LDEORB_32_MEMOP: + return ARM64_STEORB; + case ENC_STEORH_LDEORH_32_MEMOP: + return ARM64_STEORH; + case ENC_STEORL_LDEORL_32_MEMOP: + case ENC_STEORL_LDEORL_64_MEMOP: + return ARM64_STEORL; + case ENC_STEORLB_LDEORLB_32_MEMOP: + return ARM64_STEORLB; + case ENC_STEORLH_LDEORLH_32_MEMOP: + return ARM64_STEORLH; + case ENC_STG_64SPOST_LDSTTAGS: + case ENC_STG_64SPRE_LDSTTAGS: + case ENC_STG_64SOFFSET_LDSTTAGS: + return ARM64_STG; + case ENC_STGM_64BULK_LDSTTAGS: + return ARM64_STGM; + case ENC_STGP_64_LDSTPAIR_POST: + case ENC_STGP_64_LDSTPAIR_PRE: + case ENC_STGP_64_LDSTPAIR_OFF: + return ARM64_STGP; + case ENC_STLLR_SL32_LDSTORD: + case ENC_STLLR_SL64_LDSTORD: + return ARM64_STLLR; + case ENC_STLLRB_SL32_LDSTORD: + return ARM64_STLLRB; + case ENC_STLLRH_SL32_LDSTORD: + return ARM64_STLLRH; + case ENC_STLR_SL32_LDSTORD: + case ENC_STLR_SL64_LDSTORD: + return ARM64_STLR; + case ENC_STLRB_SL32_LDSTORD: + return ARM64_STLRB; + case ENC_STLRH_SL32_LDSTORD: + return ARM64_STLRH; + case ENC_STLUR_32_LDAPSTL_UNSCALED: + case ENC_STLUR_64_LDAPSTL_UNSCALED: + return ARM64_STLUR; + case ENC_STLURB_32_LDAPSTL_UNSCALED: + return ARM64_STLURB; + case ENC_STLURH_32_LDAPSTL_UNSCALED: + return ARM64_STLURH; + case ENC_STLXP_SP32_LDSTEXCLP: + case ENC_STLXP_SP64_LDSTEXCLP: + return ARM64_STLXP; + case ENC_STLXR_SR32_LDSTEXCLR: + case ENC_STLXR_SR64_LDSTEXCLR: + return ARM64_STLXR; + case ENC_STLXRB_SR32_LDSTEXCLR: + return ARM64_STLXRB; + case ENC_STLXRH_SR32_LDSTEXCLR: + return ARM64_STLXRH; + case ENC_STNP_S_LDSTNAPAIR_OFFS: + case ENC_STNP_D_LDSTNAPAIR_OFFS: + case ENC_STNP_Q_LDSTNAPAIR_OFFS: + case ENC_STNP_32_LDSTNAPAIR_OFFS: + case ENC_STNP_64_LDSTNAPAIR_OFFS: + return ARM64_STNP; + case ENC_STNT1B_Z_P_AR_S_X32_UNSCALED: + case ENC_STNT1B_Z_P_AR_D_64_UNSCALED: + case ENC_STNT1B_Z_P_BI_CONTIGUOUS: + case ENC_STNT1B_Z_P_BR_CONTIGUOUS: + return ARM64_STNT1B; + case ENC_STNT1D_Z_P_AR_D_64_UNSCALED: + case ENC_STNT1D_Z_P_BI_CONTIGUOUS: + case ENC_STNT1D_Z_P_BR_CONTIGUOUS: + return ARM64_STNT1D; + case ENC_STNT1H_Z_P_AR_S_X32_UNSCALED: + case ENC_STNT1H_Z_P_AR_D_64_UNSCALED: + case ENC_STNT1H_Z_P_BI_CONTIGUOUS: + case ENC_STNT1H_Z_P_BR_CONTIGUOUS: + return ARM64_STNT1H; + case ENC_STNT1W_Z_P_AR_S_X32_UNSCALED: + case ENC_STNT1W_Z_P_AR_D_64_UNSCALED: + case ENC_STNT1W_Z_P_BI_CONTIGUOUS: + case ENC_STNT1W_Z_P_BR_CONTIGUOUS: + return ARM64_STNT1W; + case ENC_STP_S_LDSTPAIR_POST: + case ENC_STP_D_LDSTPAIR_POST: + case ENC_STP_Q_LDSTPAIR_POST: + case ENC_STP_S_LDSTPAIR_PRE: + case ENC_STP_D_LDSTPAIR_PRE: + case ENC_STP_Q_LDSTPAIR_PRE: + case ENC_STP_S_LDSTPAIR_OFF: + case ENC_STP_D_LDSTPAIR_OFF: + case ENC_STP_Q_LDSTPAIR_OFF: + case ENC_STP_32_LDSTPAIR_POST: + case ENC_STP_64_LDSTPAIR_POST: + case ENC_STP_32_LDSTPAIR_PRE: + case ENC_STP_64_LDSTPAIR_PRE: + case ENC_STP_32_LDSTPAIR_OFF: + case ENC_STP_64_LDSTPAIR_OFF: + return ARM64_STP; + case ENC_STR_B_LDST_IMMPOST: + case ENC_STR_H_LDST_IMMPOST: + case ENC_STR_S_LDST_IMMPOST: + case ENC_STR_D_LDST_IMMPOST: + case ENC_STR_Q_LDST_IMMPOST: + case ENC_STR_B_LDST_IMMPRE: + case ENC_STR_H_LDST_IMMPRE: + case ENC_STR_S_LDST_IMMPRE: + case ENC_STR_D_LDST_IMMPRE: + case ENC_STR_Q_LDST_IMMPRE: + case ENC_STR_B_LDST_POS: + case ENC_STR_H_LDST_POS: + case ENC_STR_S_LDST_POS: + case ENC_STR_D_LDST_POS: + case ENC_STR_Q_LDST_POS: + case ENC_STR_32_LDST_IMMPOST: + case ENC_STR_64_LDST_IMMPOST: + case ENC_STR_32_LDST_IMMPRE: + case ENC_STR_64_LDST_IMMPRE: + case ENC_STR_32_LDST_POS: + case ENC_STR_64_LDST_POS: + case ENC_STR_B_LDST_REGOFF: + case ENC_STR_BL_LDST_REGOFF: + case ENC_STR_H_LDST_REGOFF: + case ENC_STR_S_LDST_REGOFF: + case ENC_STR_D_LDST_REGOFF: + case ENC_STR_Q_LDST_REGOFF: + case ENC_STR_32_LDST_REGOFF: + case ENC_STR_64_LDST_REGOFF: + case ENC_STR_P_BI_: + case ENC_STR_Z_BI_: + case ENC_STR_ZA_RI_: + return ARM64_STR; + case ENC_STRB_32_LDST_IMMPOST: + case ENC_STRB_32_LDST_IMMPRE: + case ENC_STRB_32_LDST_POS: + case ENC_STRB_32B_LDST_REGOFF: + case ENC_STRB_32BL_LDST_REGOFF: + return ARM64_STRB; + case ENC_STRH_32_LDST_IMMPOST: + case ENC_STRH_32_LDST_IMMPRE: + case ENC_STRH_32_LDST_POS: + case ENC_STRH_32_LDST_REGOFF: + return ARM64_STRH; + case ENC_STSET_LDSET_32_MEMOP: + case ENC_STSET_LDSET_64_MEMOP: + return ARM64_STSET; + case ENC_STSETB_LDSETB_32_MEMOP: + return ARM64_STSETB; + case ENC_STSETH_LDSETH_32_MEMOP: + return ARM64_STSETH; + case ENC_STSETL_LDSETL_32_MEMOP: + case ENC_STSETL_LDSETL_64_MEMOP: + return ARM64_STSETL; + case ENC_STSETLB_LDSETLB_32_MEMOP: + return ARM64_STSETLB; + case ENC_STSETLH_LDSETLH_32_MEMOP: + return ARM64_STSETLH; + case ENC_STSMAX_LDSMAX_32_MEMOP: + case ENC_STSMAX_LDSMAX_64_MEMOP: + return ARM64_STSMAX; + case ENC_STSMAXB_LDSMAXB_32_MEMOP: + return ARM64_STSMAXB; + case ENC_STSMAXH_LDSMAXH_32_MEMOP: + return ARM64_STSMAXH; + case ENC_STSMAXL_LDSMAXL_32_MEMOP: + case ENC_STSMAXL_LDSMAXL_64_MEMOP: + return ARM64_STSMAXL; + case ENC_STSMAXLB_LDSMAXLB_32_MEMOP: + return ARM64_STSMAXLB; + case ENC_STSMAXLH_LDSMAXLH_32_MEMOP: + return ARM64_STSMAXLH; + case ENC_STSMIN_LDSMIN_32_MEMOP: + case ENC_STSMIN_LDSMIN_64_MEMOP: + return ARM64_STSMIN; + case ENC_STSMINB_LDSMINB_32_MEMOP: + return ARM64_STSMINB; + case ENC_STSMINH_LDSMINH_32_MEMOP: + return ARM64_STSMINH; + case ENC_STSMINL_LDSMINL_32_MEMOP: + case ENC_STSMINL_LDSMINL_64_MEMOP: + return ARM64_STSMINL; + case ENC_STSMINLB_LDSMINLB_32_MEMOP: + return ARM64_STSMINLB; + case ENC_STSMINLH_LDSMINLH_32_MEMOP: + return ARM64_STSMINLH; + case ENC_STTR_32_LDST_UNPRIV: + case ENC_STTR_64_LDST_UNPRIV: + return ARM64_STTR; + case ENC_STTRB_32_LDST_UNPRIV: + return ARM64_STTRB; + case ENC_STTRH_32_LDST_UNPRIV: + return ARM64_STTRH; + case ENC_STUMAX_LDUMAX_32_MEMOP: + case ENC_STUMAX_LDUMAX_64_MEMOP: + return ARM64_STUMAX; + case ENC_STUMAXB_LDUMAXB_32_MEMOP: + return ARM64_STUMAXB; + case ENC_STUMAXH_LDUMAXH_32_MEMOP: + return ARM64_STUMAXH; + case ENC_STUMAXL_LDUMAXL_32_MEMOP: + case ENC_STUMAXL_LDUMAXL_64_MEMOP: + return ARM64_STUMAXL; + case ENC_STUMAXLB_LDUMAXLB_32_MEMOP: + return ARM64_STUMAXLB; + case ENC_STUMAXLH_LDUMAXLH_32_MEMOP: + return ARM64_STUMAXLH; + case ENC_STUMIN_LDUMIN_32_MEMOP: + case ENC_STUMIN_LDUMIN_64_MEMOP: + return ARM64_STUMIN; + case ENC_STUMINB_LDUMINB_32_MEMOP: + return ARM64_STUMINB; + case ENC_STUMINH_LDUMINH_32_MEMOP: + return ARM64_STUMINH; + case ENC_STUMINL_LDUMINL_32_MEMOP: + case ENC_STUMINL_LDUMINL_64_MEMOP: + return ARM64_STUMINL; + case ENC_STUMINLB_LDUMINLB_32_MEMOP: + return ARM64_STUMINLB; + case ENC_STUMINLH_LDUMINLH_32_MEMOP: + return ARM64_STUMINLH; + case ENC_STUR_B_LDST_UNSCALED: + case ENC_STUR_H_LDST_UNSCALED: + case ENC_STUR_S_LDST_UNSCALED: + case ENC_STUR_D_LDST_UNSCALED: + case ENC_STUR_Q_LDST_UNSCALED: + case ENC_STUR_32_LDST_UNSCALED: + case ENC_STUR_64_LDST_UNSCALED: + return ARM64_STUR; + case ENC_STURB_32_LDST_UNSCALED: + return ARM64_STURB; + case ENC_STURH_32_LDST_UNSCALED: + return ARM64_STURH; + case ENC_STXP_SP32_LDSTEXCLP: + case ENC_STXP_SP64_LDSTEXCLP: + return ARM64_STXP; + case ENC_STXR_SR32_LDSTEXCLR: + case ENC_STXR_SR64_LDSTEXCLR: + return ARM64_STXR; + case ENC_STXRB_SR32_LDSTEXCLR: + return ARM64_STXRB; + case ENC_STXRH_SR32_LDSTEXCLR: + return ARM64_STXRH; + case ENC_STZ2G_64SPOST_LDSTTAGS: + case ENC_STZ2G_64SPRE_LDSTTAGS: + case ENC_STZ2G_64SOFFSET_LDSTTAGS: + return ARM64_STZ2G; + case ENC_STZG_64SPOST_LDSTTAGS: + case ENC_STZG_64SPRE_LDSTTAGS: + case ENC_STZG_64SOFFSET_LDSTTAGS: + return ARM64_STZG; + case ENC_STZGM_64BULK_LDSTTAGS: + return ARM64_STZGM; + case ENC_SUB_32_ADDSUB_EXT: + case ENC_SUB_64_ADDSUB_EXT: + case ENC_SUB_32_ADDSUB_IMM: + case ENC_SUB_64_ADDSUB_IMM: + case ENC_SUB_32_ADDSUB_SHIFT: + case ENC_SUB_64_ADDSUB_SHIFT: + case ENC_SUB_ASISDSAME_ONLY: + case ENC_SUB_ASIMDSAME_ONLY: + case ENC_SUB_Z_P_ZZ_: + case ENC_SUB_Z_ZI_: + case ENC_SUB_Z_ZZ_: + return ARM64_SUB; + case ENC_SUBG_64_ADDSUB_IMMTAGS: + return ARM64_SUBG; + case ENC_SUBHN_ASIMDDIFF_N: + return ARM64_SUBHN; + //case ENC_SUBHN_ASIMDDIFF_N: + // return ARM64_SUBHN2; + case ENC_SUBHNB_Z_ZZ_: + return ARM64_SUBHNB; + case ENC_SUBHNT_Z_ZZ_: + return ARM64_SUBHNT; + case ENC_SUBP_64S_DP_2SRC: + return ARM64_SUBP; + case ENC_SUBPS_64S_DP_2SRC: + return ARM64_SUBPS; + case ENC_SUBR_Z_P_ZZ_: + case ENC_SUBR_Z_ZI_: + return ARM64_SUBR; + case ENC_SUBS_32S_ADDSUB_EXT: + case ENC_SUBS_64S_ADDSUB_EXT: + case ENC_SUBS_32S_ADDSUB_IMM: + case ENC_SUBS_64S_ADDSUB_IMM: + case ENC_SUBS_32_ADDSUB_SHIFT: + case ENC_SUBS_64_ADDSUB_SHIFT: + return ARM64_SUBS; + case ENC_SUDOT_ASIMDELEM_D: + case ENC_SUDOT_Z_ZZZI_S: + return ARM64_SUDOT; + case ENC_SUMOPA_ZA_PP_ZZ_32: + case ENC_SUMOPA_ZA_PP_ZZ_64: + return ARM64_SUMOPA; + case ENC_SUMOPS_ZA_PP_ZZ_32: + case ENC_SUMOPS_ZA_PP_ZZ_64: + return ARM64_SUMOPS; + case ENC_SUNPKHI_Z_Z_: + return ARM64_SUNPKHI; + case ENC_SUNPKLO_Z_Z_: + return ARM64_SUNPKLO; + case ENC_SUQADD_ASISDMISC_R: + case ENC_SUQADD_ASIMDMISC_R: + case ENC_SUQADD_Z_P_ZZ_: + return ARM64_SUQADD; + case ENC_SVC_EX_EXCEPTION: + return ARM64_SVC; + case ENC_SWP_32_MEMOP: + case ENC_SWP_64_MEMOP: + return ARM64_SWP; + case ENC_SWPA_32_MEMOP: + case ENC_SWPA_64_MEMOP: + return ARM64_SWPA; + case ENC_SWPAB_32_MEMOP: + return ARM64_SWPAB; + case ENC_SWPAH_32_MEMOP: + return ARM64_SWPAH; + case ENC_SWPAL_32_MEMOP: + case ENC_SWPAL_64_MEMOP: + return ARM64_SWPAL; + case ENC_SWPALB_32_MEMOP: + return ARM64_SWPALB; + case ENC_SWPALH_32_MEMOP: + return ARM64_SWPALH; + case ENC_SWPB_32_MEMOP: + return ARM64_SWPB; + case ENC_SWPH_32_MEMOP: + return ARM64_SWPH; + case ENC_SWPL_32_MEMOP: + case ENC_SWPL_64_MEMOP: + return ARM64_SWPL; + case ENC_SWPLB_32_MEMOP: + return ARM64_SWPLB; + case ENC_SWPLH_32_MEMOP: + return ARM64_SWPLH; + case ENC_SXTB_SBFM_32M_BITFIELD: + case ENC_SXTB_SBFM_64M_BITFIELD: + case ENC_SXTB_Z_P_Z_: + return ARM64_SXTB; + case ENC_SXTH_SBFM_32M_BITFIELD: + case ENC_SXTH_SBFM_64M_BITFIELD: + case ENC_SXTH_Z_P_Z_: + return ARM64_SXTH; + case ENC_SXTL_SSHLL_ASIMDSHF_L: + return ARM64_SXTL; + //case ENC_SXTL_SSHLL_ASIMDSHF_L: + // return ARM64_SXTL2; + case ENC_SXTW_SBFM_64M_BITFIELD: + case ENC_SXTW_Z_P_Z_: + return ARM64_SXTW; + case ENC_SYS_CR_SYSTEMINSTRS: + return ARM64_SYS; + case ENC_SYSL_RC_SYSTEMINSTRS: + return ARM64_SYSL; + case ENC_TBL_ASIMDTBL_L2_2: + case ENC_TBL_ASIMDTBL_L3_3: + case ENC_TBL_ASIMDTBL_L4_4: + case ENC_TBL_ASIMDTBL_L1_1: + case ENC_TBL_Z_ZZ_1: + case ENC_TBL_Z_ZZ_2: + return ARM64_TBL; + case ENC_TBNZ_ONLY_TESTBRANCH: + return ARM64_TBNZ; + case ENC_TBX_ASIMDTBL_L2_2: + case ENC_TBX_ASIMDTBL_L3_3: + case ENC_TBX_ASIMDTBL_L4_4: + case ENC_TBX_ASIMDTBL_L1_1: + case ENC_TBX_Z_ZZ_: + return ARM64_TBX; + case ENC_TBZ_ONLY_TESTBRANCH: + return ARM64_TBZ; + case ENC_TCANCEL_EX_EXCEPTION: + return ARM64_TCANCEL; + case ENC_TCOMMIT_ONLY_BARRIERS: + return ARM64_TCOMMIT; + case ENC_TLBI_SYS_CR_SYSTEMINSTRS: + return ARM64_TLBI; + case ENC_TRN1_ASIMDPERM_ONLY: + case ENC_TRN1_P_PP_: + case ENC_TRN1_Z_ZZ_: + case ENC_TRN1_Z_ZZ_Q: + return ARM64_TRN1; + case ENC_TRN2_ASIMDPERM_ONLY: + case ENC_TRN2_P_PP_: + case ENC_TRN2_Z_ZZ_: + case ENC_TRN2_Z_ZZ_Q: + return ARM64_TRN2; + case ENC_TSB_HC_HINTS: + return ARM64_TSB; + case ENC_TST_ANDS_32S_LOG_IMM: + case ENC_TST_ANDS_64S_LOG_IMM: + case ENC_TST_ANDS_32_LOG_SHIFT: + case ENC_TST_ANDS_64_LOG_SHIFT: + return ARM64_TST; + case ENC_TSTART_BR_SYSTEMRESULT: + return ARM64_TSTART; + case ENC_TTEST_BR_SYSTEMRESULT: + return ARM64_TTEST; + case ENC_UABA_ASIMDSAME_ONLY: + case ENC_UABA_Z_ZZZ_: + return ARM64_UABA; + case ENC_UABAL_ASIMDDIFF_L: + return ARM64_UABAL; + //case ENC_UABAL_ASIMDDIFF_L: + // return ARM64_UABAL2; + case ENC_UABALB_Z_ZZZ_: + return ARM64_UABALB; + case ENC_UABALT_Z_ZZZ_: + return ARM64_UABALT; + case ENC_UABD_ASIMDSAME_ONLY: + case ENC_UABD_Z_P_ZZ_: + return ARM64_UABD; + case ENC_UABDL_ASIMDDIFF_L: + return ARM64_UABDL; + //case ENC_UABDL_ASIMDDIFF_L: + // return ARM64_UABDL2; + case ENC_UABDLB_Z_ZZ_: + return ARM64_UABDLB; + case ENC_UABDLT_Z_ZZ_: + return ARM64_UABDLT; + case ENC_UADALP_ASIMDMISC_P: + case ENC_UADALP_Z_P_Z_: + return ARM64_UADALP; + case ENC_UADDL_ASIMDDIFF_L: + return ARM64_UADDL; + //case ENC_UADDL_ASIMDDIFF_L: + // return ARM64_UADDL2; + case ENC_UADDLB_Z_ZZ_: + return ARM64_UADDLB; + case ENC_UADDLP_ASIMDMISC_P: + return ARM64_UADDLP; + case ENC_UADDLT_Z_ZZ_: + return ARM64_UADDLT; + case ENC_UADDLV_ASIMDALL_ONLY: + return ARM64_UADDLV; + case ENC_UADDV_R_P_Z_: + return ARM64_UADDV; + case ENC_UADDW_ASIMDDIFF_W: + return ARM64_UADDW; + //case ENC_UADDW_ASIMDDIFF_W: + // return ARM64_UADDW2; + case ENC_UADDWB_Z_ZZ_: + return ARM64_UADDWB; + case ENC_UADDWT_Z_ZZ_: + return ARM64_UADDWT; + case ENC_UBFIZ_UBFM_32M_BITFIELD: + case ENC_UBFIZ_UBFM_64M_BITFIELD: + return ARM64_UBFIZ; + case ENC_UBFM_32M_BITFIELD: + case ENC_UBFM_64M_BITFIELD: + return ARM64_UBFM; + case ENC_UBFX_UBFM_32M_BITFIELD: + case ENC_UBFX_UBFM_64M_BITFIELD: + return ARM64_UBFX; + case ENC_UCLAMP_Z_ZZ_: + return ARM64_UCLAMP; + case ENC_UCVTF_ASISDSHF_C: + case ENC_UCVTF_ASIMDSHF_C: + case ENC_UCVTF_ASISDMISCFP16_R: + case ENC_UCVTF_ASISDMISC_R: + case ENC_UCVTF_ASIMDMISCFP16_R: + case ENC_UCVTF_ASIMDMISC_R: + case ENC_UCVTF_H32_FLOAT2FIX: + case ENC_UCVTF_S32_FLOAT2FIX: + case ENC_UCVTF_D32_FLOAT2FIX: + case ENC_UCVTF_H64_FLOAT2FIX: + case ENC_UCVTF_S64_FLOAT2FIX: + case ENC_UCVTF_D64_FLOAT2FIX: + case ENC_UCVTF_H32_FLOAT2INT: + case ENC_UCVTF_S32_FLOAT2INT: + case ENC_UCVTF_D32_FLOAT2INT: + case ENC_UCVTF_H64_FLOAT2INT: + case ENC_UCVTF_S64_FLOAT2INT: + case ENC_UCVTF_D64_FLOAT2INT: + case ENC_UCVTF_Z_P_Z_H2FP16: + case ENC_UCVTF_Z_P_Z_W2FP16: + case ENC_UCVTF_Z_P_Z_W2S: + case ENC_UCVTF_Z_P_Z_W2D: + case ENC_UCVTF_Z_P_Z_X2FP16: + case ENC_UCVTF_Z_P_Z_X2S: + case ENC_UCVTF_Z_P_Z_X2D: + return ARM64_UCVTF; + case ENC_UDF_ONLY_PERM_UNDEF: + return ARM64_UDF; + case ENC_UDIV_32_DP_2SRC: + case ENC_UDIV_64_DP_2SRC: + case ENC_UDIV_Z_P_ZZ_: + return ARM64_UDIV; + case ENC_UDIVR_Z_P_ZZ_: + return ARM64_UDIVR; + case ENC_UDOT_ASIMDELEM_D: + case ENC_UDOT_ASIMDSAME2_D: + case ENC_UDOT_Z_ZZZ_: + case ENC_UDOT_Z_ZZZI_S: + case ENC_UDOT_Z_ZZZI_D: + return ARM64_UDOT; + case ENC_UHADD_ASIMDSAME_ONLY: + case ENC_UHADD_Z_P_ZZ_: + return ARM64_UHADD; + case ENC_UHSUB_ASIMDSAME_ONLY: + case ENC_UHSUB_Z_P_ZZ_: + return ARM64_UHSUB; + case ENC_UHSUBR_Z_P_ZZ_: + return ARM64_UHSUBR; + case ENC_UMADDL_64WA_DP_3SRC: + return ARM64_UMADDL; + case ENC_UMAX_ASIMDSAME_ONLY: + case ENC_UMAX_Z_P_ZZ_: + case ENC_UMAX_Z_ZI_: + return ARM64_UMAX; + case ENC_UMAXP_ASIMDSAME_ONLY: + case ENC_UMAXP_Z_P_ZZ_: + return ARM64_UMAXP; + case ENC_UMAXV_ASIMDALL_ONLY: + case ENC_UMAXV_R_P_Z_: + return ARM64_UMAXV; + case ENC_UMIN_ASIMDSAME_ONLY: + case ENC_UMIN_Z_P_ZZ_: + case ENC_UMIN_Z_ZI_: + return ARM64_UMIN; + case ENC_UMINP_ASIMDSAME_ONLY: + case ENC_UMINP_Z_P_ZZ_: + return ARM64_UMINP; + case ENC_UMINV_ASIMDALL_ONLY: + case ENC_UMINV_R_P_Z_: + return ARM64_UMINV; + case ENC_UMLAL_ASIMDELEM_L: + case ENC_UMLAL_ASIMDDIFF_L: + return ARM64_UMLAL; + //case ENC_UMLAL_ASIMDELEM_L: + //case ENC_UMLAL_ASIMDDIFF_L: + // return ARM64_UMLAL2; + case ENC_UMLALB_Z_ZZZ_: + case ENC_UMLALB_Z_ZZZI_S: + case ENC_UMLALB_Z_ZZZI_D: + return ARM64_UMLALB; + case ENC_UMLALT_Z_ZZZ_: + case ENC_UMLALT_Z_ZZZI_S: + case ENC_UMLALT_Z_ZZZI_D: + return ARM64_UMLALT; + case ENC_UMLSL_ASIMDELEM_L: + case ENC_UMLSL_ASIMDDIFF_L: + return ARM64_UMLSL; + //case ENC_UMLSL_ASIMDELEM_L: + //case ENC_UMLSL_ASIMDDIFF_L: + // return ARM64_UMLSL2; + case ENC_UMLSLB_Z_ZZZ_: + case ENC_UMLSLB_Z_ZZZI_S: + case ENC_UMLSLB_Z_ZZZI_D: + return ARM64_UMLSLB; + case ENC_UMLSLT_Z_ZZZ_: + case ENC_UMLSLT_Z_ZZZI_S: + case ENC_UMLSLT_Z_ZZZI_D: + return ARM64_UMLSLT; + case ENC_UMMLA_ASIMDSAME2_G: + case ENC_UMMLA_Z_ZZZ_: + return ARM64_UMMLA; + case ENC_UMNEGL_UMSUBL_64WA_DP_3SRC: + return ARM64_UMNEGL; + case ENC_UMOPA_ZA_PP_ZZ_32: + case ENC_UMOPA_ZA_PP_ZZ_64: + return ARM64_UMOPA; + case ENC_UMOPS_ZA_PP_ZZ_32: + case ENC_UMOPS_ZA_PP_ZZ_64: + return ARM64_UMOPS; + case ENC_UMOV_ASIMDINS_W_W: + case ENC_UMOV_ASIMDINS_X_X: + return ARM64_UMOV; + case ENC_UMSUBL_64WA_DP_3SRC: + return ARM64_UMSUBL; + case ENC_UMULH_64_DP_3SRC: + case ENC_UMULH_Z_P_ZZ_: + case ENC_UMULH_Z_ZZ_: + return ARM64_UMULH; + case ENC_UMULL_UMADDL_64WA_DP_3SRC: + case ENC_UMULL_ASIMDELEM_L: + case ENC_UMULL_ASIMDDIFF_L: + return ARM64_UMULL; + //case ENC_UMULL_ASIMDELEM_L: + //case ENC_UMULL_ASIMDDIFF_L: + // return ARM64_UMULL2; + case ENC_UMULLB_Z_ZZ_: + case ENC_UMULLB_Z_ZZI_S: + case ENC_UMULLB_Z_ZZI_D: + return ARM64_UMULLB; + case ENC_UMULLT_Z_ZZ_: + case ENC_UMULLT_Z_ZZI_S: + case ENC_UMULLT_Z_ZZI_D: + return ARM64_UMULLT; + case ENC_UQADD_ASISDSAME_ONLY: + case ENC_UQADD_ASIMDSAME_ONLY: + case ENC_UQADD_Z_P_ZZ_: + case ENC_UQADD_Z_ZI_: + case ENC_UQADD_Z_ZZ_: + return ARM64_UQADD; + case ENC_UQDECB_R_RS_UW: + case ENC_UQDECB_R_RS_X: + return ARM64_UQDECB; + case ENC_UQDECD_R_RS_UW: + case ENC_UQDECD_R_RS_X: + case ENC_UQDECD_Z_ZS_: + return ARM64_UQDECD; + case ENC_UQDECH_R_RS_UW: + case ENC_UQDECH_R_RS_X: + case ENC_UQDECH_Z_ZS_: + return ARM64_UQDECH; + case ENC_UQDECP_R_P_R_UW: + case ENC_UQDECP_R_P_R_X: + case ENC_UQDECP_Z_P_Z_: + return ARM64_UQDECP; + case ENC_UQDECW_R_RS_UW: + case ENC_UQDECW_R_RS_X: + case ENC_UQDECW_Z_ZS_: + return ARM64_UQDECW; + case ENC_UQINCB_R_RS_UW: + case ENC_UQINCB_R_RS_X: + return ARM64_UQINCB; + case ENC_UQINCD_R_RS_UW: + case ENC_UQINCD_R_RS_X: + case ENC_UQINCD_Z_ZS_: + return ARM64_UQINCD; + case ENC_UQINCH_R_RS_UW: + case ENC_UQINCH_R_RS_X: + case ENC_UQINCH_Z_ZS_: + return ARM64_UQINCH; + case ENC_UQINCP_R_P_R_UW: + case ENC_UQINCP_R_P_R_X: + case ENC_UQINCP_Z_P_Z_: + return ARM64_UQINCP; + case ENC_UQINCW_R_RS_UW: + case ENC_UQINCW_R_RS_X: + case ENC_UQINCW_Z_ZS_: + return ARM64_UQINCW; + case ENC_UQRSHL_ASISDSAME_ONLY: + case ENC_UQRSHL_ASIMDSAME_ONLY: + case ENC_UQRSHL_Z_P_ZZ_: + return ARM64_UQRSHL; + case ENC_UQRSHLR_Z_P_ZZ_: + return ARM64_UQRSHLR; + case ENC_UQRSHRN_ASISDSHF_N: + case ENC_UQRSHRN_ASIMDSHF_N: + return ARM64_UQRSHRN; + //case ENC_UQRSHRN_ASIMDSHF_N: + // return ARM64_UQRSHRN2; + case ENC_UQRSHRNB_Z_ZI_: + return ARM64_UQRSHRNB; + case ENC_UQRSHRNT_Z_ZI_: + return ARM64_UQRSHRNT; + case ENC_UQSHL_ASISDSHF_R: + case ENC_UQSHL_ASIMDSHF_R: + case ENC_UQSHL_ASISDSAME_ONLY: + case ENC_UQSHL_ASIMDSAME_ONLY: + case ENC_UQSHL_Z_P_ZI_: + case ENC_UQSHL_Z_P_ZZ_: + return ARM64_UQSHL; + case ENC_UQSHLR_Z_P_ZZ_: + return ARM64_UQSHLR; + case ENC_UQSHRN_ASISDSHF_N: + case ENC_UQSHRN_ASIMDSHF_N: + return ARM64_UQSHRN; + //case ENC_UQSHRN_ASIMDSHF_N: + // return ARM64_UQSHRN2; + case ENC_UQSHRNB_Z_ZI_: + return ARM64_UQSHRNB; + case ENC_UQSHRNT_Z_ZI_: + return ARM64_UQSHRNT; + case ENC_UQSUB_ASISDSAME_ONLY: + case ENC_UQSUB_ASIMDSAME_ONLY: + case ENC_UQSUB_Z_P_ZZ_: + case ENC_UQSUB_Z_ZI_: + case ENC_UQSUB_Z_ZZ_: + return ARM64_UQSUB; + case ENC_UQSUBR_Z_P_ZZ_: + return ARM64_UQSUBR; + case ENC_UQXTN_ASISDMISC_N: + case ENC_UQXTN_ASIMDMISC_N: + return ARM64_UQXTN; + //case ENC_UQXTN_ASIMDMISC_N: + // return ARM64_UQXTN2; + case ENC_UQXTNB_Z_ZZ_: + return ARM64_UQXTNB; + case ENC_UQXTNT_Z_ZZ_: + return ARM64_UQXTNT; + case ENC_URECPE_ASIMDMISC_R: + case ENC_URECPE_Z_P_Z_: + return ARM64_URECPE; + case ENC_URHADD_ASIMDSAME_ONLY: + case ENC_URHADD_Z_P_ZZ_: + return ARM64_URHADD; + case ENC_URSHL_ASISDSAME_ONLY: + case ENC_URSHL_ASIMDSAME_ONLY: + case ENC_URSHL_Z_P_ZZ_: + return ARM64_URSHL; + case ENC_URSHLR_Z_P_ZZ_: + return ARM64_URSHLR; + case ENC_URSHR_ASISDSHF_R: + case ENC_URSHR_ASIMDSHF_R: + case ENC_URSHR_Z_P_ZI_: + return ARM64_URSHR; + case ENC_URSQRTE_ASIMDMISC_R: + case ENC_URSQRTE_Z_P_Z_: + return ARM64_URSQRTE; + case ENC_URSRA_ASISDSHF_R: + case ENC_URSRA_ASIMDSHF_R: + case ENC_URSRA_Z_ZI_: + return ARM64_URSRA; + case ENC_USDOT_ASIMDELEM_D: + case ENC_USDOT_ASIMDSAME2_D: + case ENC_USDOT_Z_ZZZ_S: + case ENC_USDOT_Z_ZZZI_S: + return ARM64_USDOT; + case ENC_USHL_ASISDSAME_ONLY: + case ENC_USHL_ASIMDSAME_ONLY: + return ARM64_USHL; + case ENC_USHLL_ASIMDSHF_L: + return ARM64_USHLL; + //case ENC_USHLL_ASIMDSHF_L: + // return ARM64_USHLL2; + case ENC_USHLLB_Z_ZI_: + return ARM64_USHLLB; + case ENC_USHLLT_Z_ZI_: + return ARM64_USHLLT; + case ENC_USHR_ASISDSHF_R: + case ENC_USHR_ASIMDSHF_R: + return ARM64_USHR; + case ENC_USMMLA_ASIMDSAME2_G: + case ENC_USMMLA_Z_ZZZ_: + return ARM64_USMMLA; + case ENC_USMOPA_ZA_PP_ZZ_32: + case ENC_USMOPA_ZA_PP_ZZ_64: + return ARM64_USMOPA; + case ENC_USMOPS_ZA_PP_ZZ_32: + case ENC_USMOPS_ZA_PP_ZZ_64: + return ARM64_USMOPS; + case ENC_USQADD_ASISDMISC_R: + case ENC_USQADD_ASIMDMISC_R: + case ENC_USQADD_Z_P_ZZ_: + return ARM64_USQADD; + case ENC_USRA_ASISDSHF_R: + case ENC_USRA_ASIMDSHF_R: + case ENC_USRA_Z_ZI_: + return ARM64_USRA; + case ENC_USUBL_ASIMDDIFF_L: + return ARM64_USUBL; + //case ENC_USUBL_ASIMDDIFF_L: + // return ARM64_USUBL2; + case ENC_USUBLB_Z_ZZ_: + return ARM64_USUBLB; + case ENC_USUBLT_Z_ZZ_: + return ARM64_USUBLT; + case ENC_USUBW_ASIMDDIFF_W: + return ARM64_USUBW; + //case ENC_USUBW_ASIMDDIFF_W: + // return ARM64_USUBW2; + case ENC_USUBWB_Z_ZZ_: + return ARM64_USUBWB; + case ENC_USUBWT_Z_ZZ_: + return ARM64_USUBWT; + case ENC_UUNPKHI_Z_Z_: + return ARM64_UUNPKHI; + case ENC_UUNPKLO_Z_Z_: + return ARM64_UUNPKLO; + case ENC_UXTB_UBFM_32M_BITFIELD: + case ENC_UXTB_Z_P_Z_: + return ARM64_UXTB; + case ENC_UXTH_UBFM_32M_BITFIELD: + case ENC_UXTH_Z_P_Z_: + return ARM64_UXTH; + case ENC_UXTL_USHLL_ASIMDSHF_L: + return ARM64_UXTL; + //case ENC_UXTL_USHLL_ASIMDSHF_L: + // return ARM64_UXTL2; + case ENC_UXTW_Z_P_Z_: + return ARM64_UXTW; + case ENC_UZP1_ASIMDPERM_ONLY: + case ENC_UZP1_P_PP_: + case ENC_UZP1_Z_ZZ_: + case ENC_UZP1_Z_ZZ_Q: + return ARM64_UZP1; + case ENC_UZP2_ASIMDPERM_ONLY: + case ENC_UZP2_P_PP_: + case ENC_UZP2_Z_ZZ_: + case ENC_UZP2_Z_ZZ_Q: + return ARM64_UZP2; + case ENC_WFE_HI_HINTS: + return ARM64_WFE; + case ENC_WFET_ONLY_SYSTEMINSTRSWITHREG: + return ARM64_WFET; + case ENC_WFI_HI_HINTS: + return ARM64_WFI; + case ENC_WFIT_ONLY_SYSTEMINSTRSWITHREG: + return ARM64_WFIT; + case ENC_WHILEGE_P_P_RR_: + return ARM64_WHILEGE; + case ENC_WHILEGT_P_P_RR_: + return ARM64_WHILEGT; + case ENC_WHILEHI_P_P_RR_: + return ARM64_WHILEHI; + case ENC_WHILEHS_P_P_RR_: + return ARM64_WHILEHS; + case ENC_WHILELE_P_P_RR_: + return ARM64_WHILELE; + case ENC_WHILELO_P_P_RR_: + return ARM64_WHILELO; + case ENC_WHILELS_P_P_RR_: + return ARM64_WHILELS; + case ENC_WHILELT_P_P_RR_: + return ARM64_WHILELT; + case ENC_WHILERW_P_RR_: + return ARM64_WHILERW; + case ENC_WHILEWR_P_RR_: + return ARM64_WHILEWR; + case ENC_WRFFR_F_P_: + return ARM64_WRFFR; + case ENC_XAFLAG_M_PSTATE: + return ARM64_XAFLAG; + case ENC_XAR_VVV2_CRYPTO3_IMM6: + case ENC_XAR_Z_ZZI_: + return ARM64_XAR; + case ENC_XPACD_64Z_DP_1SRC: + return ARM64_XPACD; + case ENC_XPACI_64Z_DP_1SRC: + return ARM64_XPACI; + case ENC_XPACLRI_HI_HINTS: + return ARM64_XPACLRI; + case ENC_XTN_ASIMDMISC_N: + return ARM64_XTN; + //case ENC_XTN_ASIMDMISC_N: + // return ARM64_XTN2; + case ENC_YIELD_HI_HINTS: + return ARM64_YIELD; + case ENC_ZERO_ZA_I_: + return ARM64_ZERO; + case ENC_ZIP1_ASIMDPERM_ONLY: + case ENC_ZIP1_P_PP_: + case ENC_ZIP1_Z_ZZ_: + case ENC_ZIP1_Z_ZZ_Q: + return ARM64_ZIP1; + case ENC_ZIP2_ASIMDPERM_ONLY: + case ENC_ZIP2_P_PP_: + case ENC_ZIP2_Z_ZZ_: + case ENC_ZIP2_Z_ZZ_Q: + return ARM64_ZIP2; + default: + return ARM64_ERROR; + } +} + +enum Operation enc_to_oper2(enum ENCODING enc) +{ + switch(enc) { + case ENC_ADDHN_ASIMDDIFF_N: + return ARM64_ADDHN2; + case ENC_BFCVTN_ASIMDMISC_4S: + return ARM64_BFCVTN2; + case ENC_FCVTL_ASIMDMISC_L: + return ARM64_FCVTL2; + case ENC_FCVTN_ASIMDMISC_N: + return ARM64_FCVTN2; + case ENC_FCVTXN_ASIMDMISC_N: + return ARM64_FCVTXN2; + case ENC_PMULL_ASIMDDIFF_L: + return ARM64_PMULL2; + case ENC_RADDHN_ASIMDDIFF_N: + return ARM64_RADDHN2; + case ENC_RSHRN_ASIMDSHF_N: + return ARM64_RSHRN2; + case ENC_RSUBHN_ASIMDDIFF_N: + return ARM64_RSUBHN2; + case ENC_SABAL_ASIMDDIFF_L: + return ARM64_SABAL2; + case ENC_SABDL_ASIMDDIFF_L: + return ARM64_SABDL2; + case ENC_SADDL_ASIMDDIFF_L: + return ARM64_SADDL2; + case ENC_SADDW_ASIMDDIFF_W: + return ARM64_SADDW2; + case ENC_SHLL_ASIMDMISC_S: + return ARM64_SHLL2; + case ENC_SHRN_ASIMDSHF_N: + return ARM64_SHRN2; + case ENC_SMLAL_ASIMDELEM_L: + case ENC_SMLAL_ASIMDDIFF_L: + return ARM64_SMLAL2; + case ENC_SMLSL_ASIMDELEM_L: + case ENC_SMLSL_ASIMDDIFF_L: + return ARM64_SMLSL2; + case ENC_SMULL_ASIMDELEM_L: + case ENC_SMULL_ASIMDDIFF_L: + return ARM64_SMULL2; + case ENC_SQDMLAL_ASIMDELEM_L: + case ENC_SQDMLAL_ASIMDDIFF_L: + return ARM64_SQDMLAL2; + case ENC_SQDMLSL_ASIMDELEM_L: + case ENC_SQDMLSL_ASIMDDIFF_L: + return ARM64_SQDMLSL2; + case ENC_SQDMULL_ASIMDELEM_L: + case ENC_SQDMULL_ASIMDDIFF_L: + return ARM64_SQDMULL2; + case ENC_SQRSHRN_ASIMDSHF_N: + return ARM64_SQRSHRN2; + case ENC_SQRSHRUN_ASIMDSHF_N: + return ARM64_SQRSHRUN2; + case ENC_SQSHRN_ASIMDSHF_N: + return ARM64_SQSHRN2; + case ENC_SQSHRUN_ASIMDSHF_N: + return ARM64_SQSHRUN2; + case ENC_SQXTN_ASIMDMISC_N: + return ARM64_SQXTN2; + case ENC_SQXTUN_ASIMDMISC_N: + return ARM64_SQXTUN2; + case ENC_SSHLL_ASIMDSHF_L: + return ARM64_SSHLL2; + case ENC_SSUBL_ASIMDDIFF_L: + return ARM64_SSUBL2; + case ENC_SSUBW_ASIMDDIFF_W: + return ARM64_SSUBW2; + case ENC_SUBHN_ASIMDDIFF_N: + return ARM64_SUBHN2; + case ENC_SXTL_SSHLL_ASIMDSHF_L: + return ARM64_SXTL2; + case ENC_UABAL_ASIMDDIFF_L: + return ARM64_UABAL2; + case ENC_UABDL_ASIMDDIFF_L: + return ARM64_UABDL2; + case ENC_UADDL_ASIMDDIFF_L: + return ARM64_UADDL2; + case ENC_UADDW_ASIMDDIFF_W: + return ARM64_UADDW2; + case ENC_UMLAL_ASIMDELEM_L: + case ENC_UMLAL_ASIMDDIFF_L: + return ARM64_UMLAL2; + case ENC_UMLSL_ASIMDELEM_L: + case ENC_UMLSL_ASIMDDIFF_L: + return ARM64_UMLSL2; + case ENC_UMULL_ASIMDELEM_L: + case ENC_UMULL_ASIMDDIFF_L: + return ARM64_UMULL2; + case ENC_UQRSHRN_ASIMDSHF_N: + return ARM64_UQRSHRN2; + case ENC_UQSHRN_ASIMDSHF_N: + return ARM64_UQSHRN2; + case ENC_UQXTN_ASIMDMISC_N: + return ARM64_UQXTN2; + case ENC_USHLL_ASIMDSHF_L: + return ARM64_USHLL2; + case ENC_USUBL_ASIMDDIFF_L: + return ARM64_USUBL2; + case ENC_USUBW_ASIMDDIFF_W: + return ARM64_USUBW2; + case ENC_UXTL_USHLL_ASIMDSHF_L: + return ARM64_UXTL2; + case ENC_XTN_ASIMDMISC_N: + return ARM64_XTN2; + default: + return ARM64_ERROR; + } +} |