diff options
| author | Mark Rowe <mark@vector35.com> | 2025-09-18 11:46:39 -0700 |
|---|---|---|
| committer | Mark Rowe <mark@vector35.com> | 2025-09-25 08:41:48 -0700 |
| commit | 6e1306923c60b3d6c1cefb1fcc240f1a064d6f20 (patch) | |
| tree | 57fb65f74fecfa95dd394ecc5b664512d8f87609 /arch/arm64/disassembler/format.c | |
| parent | 0deeb4a61749737b98f7946ec88b693068180e28 (diff) | |
[AArch64] Update disassembler based on 2025-06 ARM ISA data
Alongside this I also added support for decoding:
* LDR / STR (table)
* PMULLB / PMULLT
* ABS / CNT / CTZ
* SMIN / SMAX / UMIN / UMAX
* RPRFM
* PSEL
Note that while these instructions will now be disassembled, they are
not yet lifted to LLIL.
Additionally, I fixed a number of errors in the decoding of some less
commonly occurring instructions.
Diffstat (limited to 'arch/arm64/disassembler/format.c')
| -rw-r--r-- | arch/arm64/disassembler/format.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/disassembler/format.c b/arch/arm64/disassembler/format.c index b2b7a5a8..0db5ffbc 100644 --- a/arch/arm64/disassembler/format.c +++ b/arch/arm64/disassembler/format.c @@ -100,7 +100,7 @@ const char *get_operation(const Instruction *inst) return operation_to_str(inst->operation); } -static const char *ConditionString[] = { +static const char *const ConditionString[] = { "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", @@ -115,7 +115,7 @@ const char *get_condition(Condition cond) return ConditionString[cond]; } -static const char *ShiftString[] = { +static const char *const ShiftString[] = { "NONE", "lsl", "lsr", "asr", "ror", "uxtw", "sxtw", "sxtx", "uxtx", "sxtb", "sxth", "uxth", |