diff options
| author | Mark Rowe <mark@vector35.com> | 2025-10-09 09:31:15 -0700 |
|---|---|---|
| committer | Mark Rowe <mark@vector35.com> | 2025-10-15 14:10:49 -0700 |
| commit | 3f39c3fc3d5603bba111502eee26b5fbbb0077fe (patch) | |
| tree | 1bc2fc14f8a87569a4eab1f32dac269d0670dfb0 /arch/arm64/disassembler/operations.h | |
| parent | 25212cfd39f6dc45ce9030c194b6131645b76ba3 (diff) | |
[AArch64] Update disassembler based on 2025-09 ARM ISA data
Diffstat (limited to 'arch/arm64/disassembler/operations.h')
| -rw-r--r-- | arch/arm64/disassembler/operations.h | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/arch/arm64/disassembler/operations.h b/arch/arm64/disassembler/operations.h index d692c8b5..9c917b90 100644 --- a/arch/arm64/disassembler/operations.h +++ b/arch/arm64/disassembler/operations.h @@ -18,9 +18,11 @@ enum Operation { ARM64_ADDP, ARM64_ADDPL, ARM64_ADDPT, + ARM64_ADDQP, ARM64_ADDQV, ARM64_ADDS, ARM64_ADDSPL, + ARM64_ADDSUBP, ARM64_ADDSVL, ARM64_ADDV, ARM64_ADDVA, @@ -470,7 +472,9 @@ enum Operation { ARM64_FCVTXN2, ARM64_FCVTXNT, ARM64_FCVTZS, + ARM64_FCVTZSN, ARM64_FCVTZU, + ARM64_FCVTZUN, ARM64_FDIV, ARM64_FDIVR, ARM64_FDOT, @@ -567,7 +571,10 @@ enum Operation { ARM64_GCSSS2, ARM64_GCSSTR, ARM64_GCSSTTR, + ARM64_GIC, + ARM64_GICR, ARM64_GMI, + ARM64_GSB, ARM64_HINT, ARM64_HISTCNT, ARM64_HISTSEG, @@ -646,7 +653,9 @@ enum Operation { ARM64_LDADDL, ARM64_LDADDLB, ARM64_LDADDLH, + ARM64_LDAP, ARM64_LDAP1, + ARM64_LDAPP, ARM64_LDAPR, ARM64_LDAPRB, ARM64_LDAPRH, @@ -873,6 +882,7 @@ enum Operation { ARM64_LSRV, ARM64_LUTI2, ARM64_LUTI4, + ARM64_LUTI6, ARM64_MAD, ARM64_MADD, ARM64_MADDPT, @@ -880,6 +890,7 @@ enum Operation { ARM64_MATCH, ARM64_MLA, ARM64_MLAPT, + ARM64_MLBI, ARM64_MLS, ARM64_MNEG, ARM64_MOV, @@ -1102,6 +1113,7 @@ enum Operation { ARM64_SBFX, ARM64_SCLAMP, ARM64_SCVTF, + ARM64_SCVTFLT, ARM64_SDIV, ARM64_SDIVR, ARM64_SDOT, @@ -1159,6 +1171,7 @@ enum Operation { ARM64_SHRNT, ARM64_SHSUB, ARM64_SHSUBR, + ARM64_SHUH, ARM64_SLI, ARM64_SM3PARTW1, ARM64_SM3PARTW2, @@ -1349,6 +1362,7 @@ enum Operation { ARM64_STCLRL, ARM64_STCLRLB, ARM64_STCLRLH, + ARM64_STCPH, ARM64_STEOR, ARM64_STEORB, ARM64_STEORH, @@ -1373,6 +1387,7 @@ enum Operation { ARM64_STLLR, ARM64_STLLRB, ARM64_STLLRH, + ARM64_STLP, ARM64_STLR, ARM64_STLRB, ARM64_STLRH, @@ -1506,8 +1521,6 @@ enum Operation { ARM64_TBX, ARM64_TBXQ, ARM64_TBZ, - ARM64_TCANCEL, - ARM64_TCOMMIT, ARM64_TLBI, ARM64_TLBIP, ARM64_TRCIT, @@ -1515,8 +1528,6 @@ enum Operation { ARM64_TRN2, ARM64_TSB, ARM64_TST, - ARM64_TSTART, - ARM64_TTEST, ARM64_UABA, ARM64_UABAL, ARM64_UABAL2, @@ -1544,6 +1555,7 @@ enum Operation { ARM64_UBFX, ARM64_UCLAMP, ARM64_UCVTF, + ARM64_UCVTFLT, ARM64_UDF, ARM64_UDIV, ARM64_UDIVR, |