[AArch64] Update disassembler based on 2025-06 ARM ISA data

Alongside this I also added support for decoding:

* LDR / STR (table)
* PMULLB / PMULLT
* ABS / CNT / CTZ
* SMIN / SMAX / UMIN / UMAX
* RPRFM
* PSEL

Note that while these instructions will now be disassembled, they are
not yet lifted to LLIL.

Additionally, I fixed a number of errors in the decoding of some less
commonly occurring instructions.

1 files changed, 39 insertions, 1 deletions

diff --git a/arch/arm64/disassembler/pcode.h b/arch/arm64/disassembler/pcode.h
index e9410f34..b2e42265 100644
--- a/arch/arm64/disassembler/pcode.h
+++ b/arch/arm64/disassembler/pcode.h
@@ -1,6 +1,16 @@
 #include "feature_flags.h"
 
+#include <stdint.h>
+
 #define INSWORD (ctx->insword)
+#define EndOfDecode(code) \
+	{ \
+        switch (code) { \
+	    case Decode_UNDEF: return DECODE_STATUS_UNDEFINED; \
+	    case Decode_NOP: return DECODE_STATUS_END_OF_INSTRUCTION;\
+	    case Decode_OK: rc = DECODE_STATUS_OK ; break;\
+    	} \
+	}
 #define UNDEFINED \
 	{ \
 		return DECODE_STATUS_UNDEFINED; \
@@ -83,6 +93,13 @@
 #define SetBTypeNext(X)       ctx->BTypeNext = (X)
 #define Halted()              ctx->halted
 
+enum EndOfDecodeState
+{
+	Decode_UNDEF,
+ 	Decode_NOP,
+	Decode_OK,
+};
+
 enum SystemOp
 {
 	Sys_ERROR = -1,
@@ -153,6 +170,10 @@ enum SystemHintOp
 	SystemHintOp_CSDB,
 	SystemHintOp_WFET,
 	SystemHintOp_WFIT,
+	SystemHintOp_CHKFEAT,
+	SystemHintOp_CLRBHB,
+	SystemHintOp_GCSB,
+	SystemHintOp_STSHH,
 };
 
 enum ImmediateOp
@@ -293,6 +314,13 @@ enum MemOp
 	MemOp_PREFETCH
 };
 
+enum MOPSStage
+{
+	MOPSStage_Epilogue = 0,
+	MOPSStage_Main,
+	MOPSStage_Prologue
+};
+
 enum MoveWideOp
 {
 	MoveWideOp_ERROR = 0,
@@ -314,7 +342,9 @@ enum PSTATEField
 	PSTATEField_SP,
 	PSTATEField_SVCRZA,
 	PSTATEField_SVCRSM,
-	PSTATEField_SVCRSMZA
+	PSTATEField_SVCRSMZA,
+	PSTATEField_ALLINT,
+	PSTATEField_PM,
 };
 
 enum SVECmp
@@ -394,6 +424,7 @@ enum Unpredictable
 	Unpredictable_DBGxVR_RESS,
 	Unpredictable_WFxTDEBUG,
 	Unpredictable_LS64UNSUPPORTED,
+	Unpredictable_LSE128OVERLAP,
 };
 
 typedef struct DecodeBitMasks_ReturnType_
@@ -403,7 +434,13 @@ typedef struct DecodeBitMasks_ReturnType_
 } DecodeBitMasks_ReturnType;
 
 int HighestSetBit(uint64_t x);
+int HighestSetBitNZ(uint64_t x);
 int LowestSetBit(uint64_t x);
+int LowestSetBitNZ(uint64_t x);
+
+static inline int MaxImplementedAnyVL(void) { return 2048; }
+static inline int MaxImplementedSVL(void) { return 2048; }
+static inline int MaxImplementedVL(void) { return 2048; }
 
 bool BFXPreferred(uint32_t sf, uint32_t uns, uint32_t imms, uint32_t immr);
 int BitCount(uint32_t x);
@@ -441,6 +478,7 @@ uint64_t VFPExpandImm(uint8_t imm8, unsigned width);
 #define EL3 3
 bool EL2Enabled(void);
 bool ELUsingAArch32(uint8_t);
+bool HaveEL(uint8_t);
 
 uint64_t FPOne(bool sign, int width);
 uint64_t FPTwo(bool sign, int width);