diff options
| author | Mark Rowe <mark@vector35.com> | 2025-09-18 11:46:39 -0700 |
|---|---|---|
| committer | Mark Rowe <mark@vector35.com> | 2025-09-25 08:41:48 -0700 |
| commit | 6e1306923c60b3d6c1cefb1fcc240f1a064d6f20 (patch) | |
| tree | 57fb65f74fecfa95dd394ecc5b664512d8f87609 /arch/arm64/disassembler/regs.h | |
| parent | 0deeb4a61749737b98f7946ec88b693068180e28 (diff) | |
[AArch64] Update disassembler based on 2025-06 ARM ISA data
Alongside this I also added support for decoding:
* LDR / STR (table)
* PMULLB / PMULLT
* ABS / CNT / CTZ
* SMIN / SMAX / UMIN / UMAX
* RPRFM
* PSEL
Note that while these instructions will now be disassembled, they are
not yet lifted to LLIL.
Additionally, I fixed a number of errors in the decoding of some less
commonly occurring instructions.
Diffstat (limited to 'arch/arm64/disassembler/regs.h')
| -rw-r--r-- | arch/arm64/disassembler/regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/disassembler/regs.h b/arch/arm64/disassembler/regs.h index e07fe094..6da54ada 100644 --- a/arch/arm64/disassembler/regs.h +++ b/arch/arm64/disassembler/regs.h @@ -1333,6 +1333,7 @@ enum Register REG_PF29, REG_PF30, REG_PF31, + REG_ZT0, REG_END }; |