[aarch64] Updating Aarch64 system registers to 2024-12 spec, fix MSR/MRS lifting to use ReadMSR/WriteMSR intrinsics that take enums, removing the sysregs from the register list of the architecture

* sysregs are no longer registers, add enum for TLBI and AT operands
* add erroneously missing cases for unsupported encodings, add enum for DC operands

1 files changed, 1497 insertions, 0 deletions

diff --git a/arch/arm64/disassembler/sysregs_gen.c b/arch/arm64/disassembler/sysregs_gen.c
new file mode 100644
index 00000000..0ef69869
--- /dev/null
+++ b/arch/arm64/disassembler/sysregs_gen.c
@@ -0,0 +1,1497 @@
+#include <stddef.h>
+
+#include "sysregs_gen.h"
+
+/* must parallel has_system_register_name() from the decode side */
+bool has_system_register_name(enum SystemReg sr)
+{
+	switch(sr) {
+		case REG_EDSCR:
+		case REG_EDPRSR:
+		case REG_UAOIMM:
+		case REG_PANIMM:
+		case REG_SPSELIMM:
+		case REG_DITIMM:
+		case REG_SVCRIMM:
+		case REG_ICIALLUIS:
+		case REG_ICIALLU:
+		case REG_DCIVAC:
+		case REG_DCISW:
+		case REG_ATS1E1R:
+		case REG_ATS1E1W:
+		case REG_ATS1E0R:
+		case REG_ATS1E0W:
+		case REG_DCCSW:
+		case REG_DCCISW:
+		case REG_TLBIVMALLE1IS:
+		case REG_TLBIVAE1IS:
+		case REG_TLBIASIDE1IS:
+		case REG_TLBIVAAE1IS:
+		case REG_TLBIVALE1IS:
+		case REG_TLBIVAALE1IS:
+		case REG_TLBIVMALLE1:
+		case REG_TLBIVAE1:
+		case REG_TLBIASIDE1:
+		case REG_TLBIVAAE1:
+		case REG_TLBIVALE1:
+		case REG_TLBIVAALE1:
+		case REG_DCZVA:
+		case REG_ICIVAU:
+		case REG_DCCVAC:
+		case REG_DCCVAU:
+		case REG_DCCIVAC:
+		case REG_ATS1E2R:
+		case REG_ATS1E2W:
+		case REG_ATS12E1R:
+		case REG_ATS12E1W:
+		case REG_ATS12E0R:
+		case REG_ATS12E0W:
+		case REG_TLBIIPAS2E1IS:
+		case REG_TLBIIPAS2LE1IS:
+		case REG_TLBIALLE2IS:
+		case REG_TLBIVAE2IS:
+		case REG_TLBIALLE1IS:
+		case REG_TLBIVALE2IS:
+		case REG_TLBIVMALLS12E1IS:
+		case REG_TLBIIPAS2E1:
+		case REG_TLBIIPAS2LE1:
+		case REG_TLBIALLE2:
+		case REG_TLBIVAE2:
+		case REG_TLBIALLE1:
+		case REG_TLBIVALE2:
+		case REG_TLBIVMALLS12E1:
+		case REG_ATS1E3R:
+		case REG_ATS1E3W:
+		case REG_TLBIALLE3IS:
+		case REG_TLBIVAE3IS:
+		case REG_TLBIVALE3IS:
+		case REG_TLBIALLE3:
+		case REG_TLBIVAE3:
+		case REG_TLBIVALE3:
+		case REG_OSDTRRX_EL1:
+		case REG_DBGBVR0_EL1:
+		case REG_DBGBCR0_EL1:
+		case REG_DBGWVR0_EL1:
+		case REG_DBGWCR0_EL1:
+		case REG_DBGBVR1_EL1:
+		case REG_DBGBCR1_EL1:
+		case REG_DBGWVR1_EL1:
+		case REG_DBGWCR1_EL1:
+		case REG_MDCCINT_EL1:
+		case REG_MDSCR_EL1:
+		case REG_DBGBVR2_EL1:
+		case REG_DBGBCR2_EL1:
+		case REG_DBGWVR2_EL1:
+		case REG_DBGWCR2_EL1:
+		case REG_OSDTRTX_EL1:
+		case REG_DBGBVR3_EL1:
+		case REG_DBGBCR3_EL1:
+		case REG_DBGWVR3_EL1:
+		case REG_DBGWCR3_EL1:
+		case REG_DBGBVR4_EL1:
+		case REG_DBGBCR4_EL1:
+		case REG_DBGWVR4_EL1:
+		case REG_DBGWCR4_EL1:
+		case REG_DBGBVR5_EL1:
+		case REG_DBGBCR5_EL1:
+		case REG_DBGWVR5_EL1:
+		case REG_DBGWCR5_EL1:
+		case REG_DBGWFAR:
+		case REG_OSECCR_EL1:
+		case REG_DBGBVR6_EL1:
+		case REG_DBGBCR6_EL1:
+		case REG_DBGWVR6_EL1:
+		case REG_DBGWCR6_EL1:
+		case REG_DBGBVR7_EL1:
+		case REG_DBGBCR7_EL1:
+		case REG_DBGWVR7_EL1:
+		case REG_DBGWCR7_EL1:
+		case REG_DBGBVR8_EL1:
+		case REG_DBGBCR8_EL1:
+		case REG_DBGWVR8_EL1:
+		case REG_DBGWCR8_EL1:
+		case REG_DBGBVR9_EL1:
+		case REG_DBGBCR9_EL1:
+		case REG_DBGWVR9_EL1:
+		case REG_DBGWCR9_EL1:
+		case REG_DBGBVR10_EL1:
+		case REG_DBGBCR10_EL1:
+		case REG_DBGWVR10_EL1:
+		case REG_DBGWCR10_EL1:
+		case REG_DBGBVR11_EL1:
+		case REG_DBGBCR11_EL1:
+		case REG_DBGWVR11_EL1:
+		case REG_DBGWCR11_EL1:
+		case REG_DBGBVR12_EL1:
+		case REG_DBGBCR12_EL1:
+		case REG_DBGWVR12_EL1:
+		case REG_DBGWCR12_EL1:
+		case REG_DBGBVR13_EL1:
+		case REG_DBGBCR13_EL1:
+		case REG_DBGWVR13_EL1:
+		case REG_DBGWCR13_EL1:
+		case REG_DBGBVR14_EL1:
+		case REG_DBGBCR14_EL1:
+		case REG_DBGWVR14_EL1:
+		case REG_DBGWCR14_EL1:
+		case REG_DBGBVR15_EL1:
+		case REG_DBGBCR15_EL1:
+		case REG_DBGWVR15_EL1:
+		case REG_DBGWCR15_EL1:
+		case REG_MDRAR_EL1:
+		case REG_OSLAR_EL1:
+		case REG_OSLSR_EL1:
+		case REG_OSDLR_EL1:
+		case REG_DBGPRCR_EL1:
+		case REG_CLAIMSET_EL1:
+		case REG_CLAIMCLR_EL1:
+		case REG_AUTHSTAT_EL1:
+		case REG_TRCTRACEIDR:
+		case REG_TRCVICTLR:
+		case REG_TRCSEQEVR0:
+		case REG_TRCCNTRLDVR0:
+		case REG_TRCIMSPEC0:
+		case REG_TRCPRGCTLR:
+		case REG_TRCQCTLR:
+		case REG_TRCVIIECTLR:
+		case REG_TRCSEQEVR1:
+		case REG_TRCCNTRLDVR1:
+		case REG_TRCIMSPEC1:
+		case REG_TRCPROCSELR:
+		case REG_TRCVISSCTLR:
+		case REG_TRCSEQEVR2:
+		case REG_TRCCNTRLDVR2:
+		case REG_TRCIMSPEC2:
+		case REG_TRCVIPCSSCTLR:
+		case REG_TRCCNTRLDVR3:
+		case REG_TRCIMSPEC3:
+		case REG_TRCCONFIGR:
+		case REG_TRCCNTCTLR0:
+		case REG_TRCIMSPEC4:
+		case REG_TRCCNTCTLR1:
+		case REG_TRCIMSPEC5:
+		case REG_TRCAUXCTLR:
+		case REG_TRCSEQRSTEVR:
+		case REG_TRCCNTCTLR2:
+		case REG_TRCIMSPEC6:
+		case REG_TRCSEQSTR:
+		case REG_TRCCNTCTLR3:
+		case REG_TRCIMSPEC7:
+		case REG_TRCEVENTCTL0R:
+		case REG_TRCVDCTLR:
+		case REG_TRCEXTINSELR:
+		case REG_TRCCNTVR0:
+		case REG_TRCEVENTCTL1R:
+		case REG_TRCVDSACCTLR:
+		case REG_TRCEXTINSELR1:
+		case REG_TRCCNTVR1:
+		case REG_TRCRSR:
+		case REG_TRCVDARCCTLR:
+		case REG_TRCEXTINSELR2:
+		case REG_TRCCNTVR2:
+		case REG_TRCSTALLCTLR:
+		case REG_TRCEXTINSELR3:
+		case REG_TRCCNTVR3:
+		case REG_TRCTSCTLR:
+		case REG_TRCSYNCPR:
+		case REG_TRCCCCTLR:
+		case REG_TRCBBCTLR:
+		case REG_TRCRSCTLR16:
+		case REG_TRCSSCCR0:
+		case REG_TRCSSPCICR0:
+		case REG_TRCOSLAR:
+		case REG_TRCRSCTLR17:
+		case REG_TRCSSCCR1:
+		case REG_TRCSSPCICR1:
+		case REG_TRCRSCTLR2:
+		case REG_TRCRSCTLR18:
+		case REG_TRCSSCCR2:
+		case REG_TRCSSPCICR2:
+		case REG_TRCRSCTLR3:
+		case REG_TRCRSCTLR19:
+		case REG_TRCSSCCR3:
+		case REG_TRCSSPCICR3:
+		case REG_TRCRSCTLR4:
+		case REG_TRCRSCTLR20:
+		case REG_TRCSSCCR4:
+		case REG_TRCSSPCICR4:
+		case REG_TRCPDCR:
+		case REG_TRCRSCTLR5:
+		case REG_TRCRSCTLR21:
+		case REG_TRCSSCCR5:
+		case REG_TRCSSPCICR5:
+		case REG_TRCRSCTLR6:
+		case REG_TRCRSCTLR22:
+		case REG_TRCSSCCR6:
+		case REG_TRCSSPCICR6:
+		case REG_TRCRSCTLR7:
+		case REG_TRCRSCTLR23:
+		case REG_TRCSSCCR7:
+		case REG_TRCSSPCICR7:
+		case REG_TRCRSCTLR8:
+		case REG_TRCRSCTLR24:
+		case REG_TRCSSCSR0:
+		case REG_TRCRSCTLR9:
+		case REG_TRCRSCTLR25:
+		case REG_TRCSSCSR1:
+		case REG_TRCRSCTLR10:
+		case REG_TRCRSCTLR26:
+		case REG_TRCSSCSR2:
+		case REG_TRCRSCTLR11:
+		case REG_TRCRSCTLR27:
+		case REG_TRCSSCSR3:
+		case REG_TRCRSCTLR12:
+		case REG_TRCRSCTLR28:
+		case REG_TRCSSCSR4:
+		case REG_TRCRSCTLR13:
+		case REG_TRCRSCTLR29:
+		case REG_TRCSSCSR5:
+		case REG_TRCRSCTLR14:
+		case REG_TRCRSCTLR30:
+		case REG_TRCSSCSR6:
+		case REG_TRCRSCTLR15:
+		case REG_TRCRSCTLR31:
+		case REG_TRCSSCSR7:
+		case REG_TRCACVR0:
+		case REG_TRCACVR8:
+		case REG_TRCACATR0:
+		case REG_TRCACATR8:
+		case REG_TRCDVCVR0:
+		case REG_TRCDVCVR4:
+		case REG_TRCDVCMR0:
+		case REG_TRCDVCMR4:
+		case REG_TRCACVR1:
+		case REG_TRCACVR9:
+		case REG_TRCACATR1:
+		case REG_TRCACATR9:
+		case REG_TRCACVR2:
+		case REG_TRCACVR10:
+		case REG_TRCACATR2:
+		case REG_TRCACATR10:
+		case REG_TRCDVCVR1:
+		case REG_TRCDVCVR5:
+		case REG_TRCDVCMR1:
+		case REG_TRCDVCMR5:
+		case REG_TRCACVR3:
+		case REG_TRCACVR11:
+		case REG_TRCACATR3:
+		case REG_TRCACATR11:
+		case REG_TRCACVR4:
+		case REG_TRCACVR12:
+		case REG_TRCACATR4:
+		case REG_TRCACATR12:
+		case REG_TRCDVCVR2:
+		case REG_TRCDVCVR6:
+		case REG_TRCDVCMR2:
+		case REG_TRCDVCMR6:
+		case REG_TRCACVR5:
+		case REG_TRCACVR13:
+		case REG_TRCACATR5:
+		case REG_TRCACATR13:
+		case REG_TRCACVR6:
+		case REG_TRCACVR14:
+		case REG_TRCACATR6:
+		case REG_TRCACATR14:
+		case REG_TRCDVCVR3:
+		case REG_TRCDVCVR7:
+		case REG_TRCDVCMR3:
+		case REG_TRCDVCMR7:
+		case REG_TRCACVR7:
+		case REG_TRCACVR15:
+		case REG_TRCACATR7:
+		case REG_TRCACATR15:
+		case REG_TRCCIDCVR0:
+		case REG_TRCVMIDCVR0:
+		case REG_TRCCIDCCTLR0:
+		case REG_TRCCIDCCTLR1:
+		case REG_TRCCIDCVR1:
+		case REG_TRCVMIDCVR1:
+		case REG_TRCVMIDCCTLR0:
+		case REG_TRCVMIDCCTLR1:
+		case REG_TRCCIDCVR2:
+		case REG_TRCVMIDCVR2:
+		case REG_TRCCIDCVR3:
+		case REG_TRCVMIDCVR3:
+		case REG_TRCCIDCVR4:
+		case REG_TRCVMIDCVR4:
+		case REG_TRCCIDCVR5:
+		case REG_TRCVMIDCVR5:
+		case REG_TRCCIDCVR6:
+		case REG_TRCVMIDCVR6:
+		case REG_TRCCIDCVR7:
+		case REG_TRCVMIDCVR7:
+		case REG_TRCITCTRL:
+		case REG_TRCCLAIMSET:
+		case REG_TRCCLAIMCLR:
+		case REG_TRCLAR:
+		case REG_TEECR32_EL1:
+		case REG_TEEHBR32_EL1:
+		case REG_MDCCSR_EL0:
+		case REG_MDDTR_EL0:
+		case REG_MDDTRTX_EL0:
+		case REG_DBGVCR32_EL2:
+		case REG_MIDR_EL1:
+		case REG_MPIDR_EL1:
+		case REG_REVIDR_EL1:
+		case REG_ID_PFR0_EL1:
+		case REG_ID_PFR1_EL1:
+		case REG_ID_DFR0_EL1:
+		case REG_ID_AFR0_EL1:
+		case REG_ID_MMFR0_EL1:
+		case REG_ID_MMFR1_EL1:
+		case REG_ID_MMFR2_EL1:
+		case REG_ID_MMFR3_EL1:
+		case REG_ID_ISAR0_EL1:
+		case REG_ID_ISAR1_EL1:
+		case REG_ID_ISAR2_EL1:
+		case REG_ID_ISAR3_EL1:
+		case REG_ID_ISAR4_EL1:
+		case REG_ID_ISAR5_EL1:
+		case REG_ID_MMFR4_EL1:
+		case REG_ID_ISAR6_EL1:
+		case REG_MVFR0_EL1:
+		case REG_MVFR1_EL1:
+		case REG_MVFR2_EL1:
+		case REG_ID_AA32RES3_EL1:
+		case REG_ID_PFR2_EL1:
+		case REG_ID_AA32RES5_EL1:
+		case REG_ID_AA32RES6_EL1:
+		case REG_ID_AA32RES7_EL1:
+		case REG_ID_AA64PFR0_EL1:
+		case REG_ID_AA64PFR1_EL1:
+		case REG_ID_AA64PFR2_EL1:
+		case REG_ID_AA64PFR3_EL1:
+		case REG_ID_AA64ZFR0_EL1:
+		case REG_ID_AA64SMFR0_EL1:
+		case REG_ID_AA64ZFR2_EL1:
+		case REG_ID_AA64ZFR3_EL1:
+		case REG_ID_AA64DFR0_EL1:
+		case REG_ID_AA64DFR1_EL1:
+		case REG_ID_AA64DFR2_EL1:
+		case REG_ID_AA64DFR3_EL1:
+		case REG_ID_AA64AFR0_EL1:
+		case REG_ID_AA64AFR1_EL1:
+		case REG_ID_AA64AFR2_EL1:
+		case REG_ID_AA64AFR3_EL1:
+		case REG_ID_AA64ISAR0_EL1:
+		case REG_ID_AA64ISAR1_EL1:
+		case REG_ID_AA64ISAR2_EL1:
+		case REG_ID_AA64ISAR3_EL1:
+		case REG_ID_AA64ISAR4_EL1:
+		case REG_ID_AA64ISAR5_EL1:
+		case REG_ID_AA64ISAR6_EL1:
+		case REG_ID_AA64ISAR7_EL1:
+		case REG_ID_AA64MMFR0_EL1:
+		case REG_ID_AA64MMFR1_EL1:
+		case REG_ID_AA64MMFR2_EL1:
+		case REG_ID_AA64MMFR3_EL1:
+		case REG_ID_AA64MMFR4_EL1:
+		case REG_ID_AA64MMFR5_EL1:
+		case REG_ID_AA64MMFR6_EL1:
+		case REG_ID_AA64MMFR7_EL1:
+		case REG_SCTLR_EL21:
+		case REG_ACTLR_EL21:
+		case REG_CPTR_EL21:
+		case REG_RGSR_EL1:
+		case REG_GCR_EL1:
+		case REG_TRFCR_EL1:
+		case REG_SMPRI_EL1:
+		case REG_SMCR_EL21:
+		case REG_TTBR0_EL21:
+		case REG_TTBR1_EL21:
+		case REG_TCR_EL21:
+		case REG_APIAKEYLO_EL21:
+		case REG_APIAKEYHI_EL21:
+		case REG_APIBKEYLO_EL21:
+		case REG_APIBKEYHI_EL21:
+		case REG_APDAKEYLO_EL21:
+		case REG_APDAKEYHI_EL21:
+		case REG_APDBKEYLO_EL21:
+		case REG_APDBKEYHI_EL21:
+		case REG_APGAKEYLO_EL21:
+		case REG_APGAKEYHI_EL21:
+		case REG_SPSR_EL21:
+		case REG_ELR_EL21:
+		case REG_SP_EL0:
+		case REG_SPSEL:
+		case REG_NESTEDCURRENTEL:
+		case REG_PAN:
+		case REG_UAO:
+		case REG_ICV_PMR_EL1:
+		case REG_AFSR0_EL21:
+		case REG_AFSR1_EL21:
+		case REG_ESR_EL21:
+		case REG_ERRIDR_EL1:
+		case REG_ERRSELR_EL1:
+		case REG_ERXCTLR_EL1:
+		case REG_ERXSTATUS_EL1:
+		case REG_ERXADDR_EL1:
+		case REG_ERXPFGCTL_EL1:
+		case REG_ERXPFGCDN_EL1:
+		case REG_ERXMISC0_EL1:
+		case REG_ERXMISC1_EL1:
+		case REG_ERXMISC2_EL1:
+		case REG_ERXMISC3_EL1:
+		case REG_ERXTS_EL1:
+		case REG_TFSR_EL1:
+		case REG_TFSRE0_EL1:
+		case REG_FAR_EL21:
+		case REG_PAR_EL1:
+		case REG_PMSCR_EL1:
+		case REG_PMSICR_EL1:
+		case REG_PMSIRR_EL1:
+		case REG_PMSFCR_EL1:
+		case REG_PMSEVFR_EL1:
+		case REG_PMSLATFR_EL1:
+		case REG_PMSIDR_EL1:
+		case REG_PMBLIMITR_EL1:
+		case REG_PMBPTR_EL1:
+		case REG_PMBSR_EL1:
+		case REG_PMBIDR_EL1:
+		case REG_TRBLIMITR_EL1:
+		case REG_TRBPTR_EL1:
+		case REG_TRBBASER_EL1:
+		case REG_TRBSR_EL1:
+		case REG_TRBMAR_EL1:
+		case REG_TRBTRG_EL1:
+		case REG_PMINTENSET_EL1:
+		case REG_PMINTENCLR_EL1:
+		case REG_PMMIR_EL1:
+		case REG_MAIR_EL21:
+		case REG_AMAIR_EL21:
+		case REG_LORSA_EL1:
+		case REG_LOREA_EL1:
+		case REG_LORN_EL1:
+		case REG_LORC_EL1:
+		case REG_LORID_EL1:
+		case REG_MPAM1_EL1:
+		case REG_MPAM0_EL1:
+		case REG_CTRR_C_LWR_EL21:
+		case REG_CTRR_C_UPR_EL21:
+		case REG_CTRR_D_LWR_EL21:
+		case REG_CTRR_D_UPR_EL21:
+		case REG_CTRR_C_LWR_EL12:
+		case REG_CTRR_C_UPR_EL12:
+		case REG_CTRR_D_LWR_EL12:
+		case REG_CTRR_D_UPR_EL12:
+		case REG_CTRR_C_LWR_EL2:
+		case REG_CTRR_C_UPR_EL2:
+		case REG_CTRR_D_LWR_EL2:
+		case REG_CTRR_D_UPR_EL2:
+		case REG_CTRR_C_CTL_EL21:
+		case REG_CTRR_D_CTL_EL21:
+		case REG_CTRR_C_CTL_EL12:
+		case REG_CTRR_D_CTL_EL12:
+		case REG_CTRR_C_CTL_EL2:
+		case REG_CTRR_D_CTL_EL2:
+		case REG_CTXR_A_LWR_EL21:
+		case REG_CTXR_A_UPR_EL21:
+		case REG_CTXR_B_LWR_EL21:
+		case REG_CTXR_B_UPR_EL21:
+		case REG_CTXR_C_LWR_EL21:
+		case REG_CTXR_C_UPR_EL21:
+		case REG_CTXR_D_LWR_EL21:
+		case REG_CTXR_D_UPR_EL21:
+		case REG_CTXR_A_LWR_EL12:
+		case REG_CTXR_A_UPR_EL12:
+		case REG_CTXR_B_LWR_EL12:
+		case REG_CTXR_B_UPR_EL12:
+		case REG_CTXR_C_LWR_EL12:
+		case REG_CTXR_C_UPR_EL12:
+		case REG_CTXR_D_LWR_EL12:
+		case REG_CTXR_D_UPR_EL12:
+		case REG_CTXR_A_LWR_EL2:
+		case REG_CTXR_A_UPR_EL2:
+		case REG_CTXR_B_LWR_EL2:
+		case REG_CTXR_B_UPR_EL2:
+		case REG_CTXR_C_LWR_EL2:
+		case REG_CTXR_C_UPR_EL2:
+		case REG_CTXR_D_LWR_EL2:
+		case REG_CTXR_D_UPR_EL2:
+		case REG_CTXR_A_CTL_EL21:
+		case REG_CTXR_B_CTL_EL21:
+		case REG_CTXR_C_CTL_EL21:
+		case REG_CTXR_D_CTL_EL21:
+		case REG_CTXR_A_CTL_EL12:
+		case REG_CTXR_B_CTL_EL12:
+		case REG_CTXR_C_CTL_EL12:
+		case REG_CTXR_D_CTL_EL12:
+		case REG_CTXR_A_CTL_EL2:
+		case REG_CTXR_B_CTL_EL2:
+		case REG_CTXR_C_CTL_EL2:
+		case REG_CTXR_D_CTL_EL2:
+		case REG_ACC_CTRR_C_LWR_EL2:
+		case REG_ACC_CTRR_C_UPR_EL2:
+		case REG_ACC_CTRR_D_LWR_EL2:
+		case REG_ACC_CTRR_D_UPR_EL2:
+		case REG_ACC_CTXR_A_LWR_EL2:
+		case REG_ACC_CTXR_A_UPR_EL2:
+		case REG_ACC_CTXR_B_LWR_EL2:
+		case REG_ACC_CTXR_B_UPR_EL2:
+		case REG_ACC_CTXR_C_LWR_EL2:
+		case REG_ACC_CTXR_C_UPR_EL2:
+		case REG_ACC_CTXR_D_LWR_EL2:
+		case REG_ACC_CTXR_D_UPR_EL2:
+		case REG_ACC_CTRR_C_CTL_EL2:
+		case REG_ACC_CTRR_D_CTL_EL2:
+		case REG_ACC_CTXR_A_CTL_EL2:
+		case REG_ACC_CTXR_B_CTL_EL2:
+		case REG_ACC_CTXR_C_CTL_EL2:
+		case REG_ACC_CTXR_D_CTL_EL2:
+		case REG_VBAR_EL21:
+		case REG_RVBAR_EL1:
+		case REG_RMR_EL1:
+		case REG_ISR_EL1:
+		case REG_DISR_EL1:
+		case REG_ICV_IAR0_EL1:
+		case REG_ICV_EOIR0_EL1:
+		case REG_ICV_HPPIR0_EL1:
+		case REG_ICV_BPR0_EL1:
+		case REG_ICC_AP0R0_EL1:
+		case REG_ICC_AP0R1_EL1:
+		case REG_ICC_AP0R2_EL1:
+		case REG_ICC_AP0R3_EL1:
+		case REG_ICC_AP1R0_EL1:
+		case REG_ICC_AP1R1_EL1:
+		case REG_ICC_AP1R2_EL1:
+		case REG_ICC_AP1R3_EL1:
+		case REG_ICV_DIR_EL1:
+		case REG_ICV_RPR_EL1:
+		case REG_ICC_SGI1R_EL1:
+		case REG_ICC_ASGI1R_EL1:
+		case REG_ICC_SGI0R_EL1:
+		case REG_ICV_IAR1_EL1:
+		case REG_ICV_EOIR1_EL1:
+		case REG_ICV_HPPIR1_EL1:
+		case REG_ICV_BPR1_EL1:
+		case REG_ICV_CTLR_EL1:
+		case REG_ICC_SRE_EL1:
+		case REG_ICV_IGRPEN0_EL1:
+		case REG_ICV_IGRPEN1_EL1:
+		case REG_ICC_SEIEN_EL1:
+		case REG_CONTEXTIDR_EL21:
+		case REG_TPIDR_EL1:
+		case REG_SCXTNUM_EL21:
+		case REG_REDIR_CNTKCTL_EL1:
+		case REG_HID0:
+		case REG_HID25:
+		case REG_HID26:
+		case REG_HID27:
+		case REG_HID28:
+		case REG_HID29:
+		case REG_HID34:
+		case REG_HID1:
+		case REG_HID21:
+		case REG_BIUVCSCUPCMDCRD:
+		case REG_BIUVCSCUPDATCRD:
+		case REG_HID2:
+		case REG_HID30:
+		case REG_HID31:
+		case REG_HID32:
+		case REG_HID33:
+		case REG_HID3:
+		case REG_BIUVCSCUPCMDCRDC2:
+		case REG_BIUVCSCUPDATCRDC2:
+		case REG_HID4:
+		case REG_HID5:
+		case REG_HID6:
+		case REG_HID7:
+		case REG_HID8:
+		case REG_HID9:
+		case REG_HID10:
+		case REG_BLOCK_CMAINT_CFG:
+		case REG_HID11:
+		case REG_HID18:
+		case REG_HID36:
+		case REG_HID37:
+		case REG_HID12:
+		case REG_HID15:
+		case REG_HID19:
+		case REG_BIU_TLIMIT:
+		case REG_HID13:
+		case REG_HID_RCTX_G0CTL:
+		case REG_HID_RCTX_G1CTL:
+		case REG_HID14:
+		case REG_HID16:
+		case REG_LLC_WRR2:
+		case REG_BIU_AFI_CFG:
+		case REG_HID17:
+		case REG_HID24:
+		case REG_HID35:
+		case REG_CCSIDRPL1_I_EL1:
+		case REG_CLIDR_EL1:
+		case REG_SMIDR_EL1:
+		case REG_AIDR_EL1:
+		case REG_PMCR0_EL1:
+		case REG_APPL_CONTEXTPTR:
+		case REG_LD_LATPROF_CTL_EL21:
+		case REG_AON_CPU_MSTALL_CTL01_EL1:
+		case REG_PM_MEMFLT_CTL23_EL1:
+		case REG_REDIR_ACNTV_CTL_EL0:
+		case REG_LCL_ACNTVCTSS_NOREDIR_EL0:
+		case REG_PMCR1_EL21:
+		case REG_LD_LATPROF_CTR_EL1:
+		case REG_AON_CPU_MSTALL_CTL23_EL1:
+		case REG_PM_MEMFLT_CTL45_EL1:
+		case REG_AGTCNTRDIR_EL21:
+		case REG_AGTCNTKCTL_NOREDIR_EL1:
+		case REG_PMCR2_EL1:
+		case REG_LD_LATPROF_STS_EL1:
+		case REG_AON_CPU_MSTALL_CTL45_EL1:
+		case REG_REDIR_ACNTHP_CVAL_EL2:
+		case REG_LCL_CNTVCT_NOREDIR_EL0:
+		case REG_AGTCNTP_CVAL_NOREDIR_EL0:
+		case REG_PMCR3_EL1:
+		case REG_LD_LATPROF_INF_EL1:
+		case REG_AON_CPU_MSTALL_CTL67_EL1:
+		case REG_REDIR_ACNTHP_TVAL_EL2:
+		case REG_LCL_CNTPCTSS_NOREDIR_EL0:
+		case REG_AGTCNTP_TVAL_NOREDIR_EL0:
+		case REG_PMCR4_EL1:
+		case REG_LD_LATPROF_CTL_EL2:
+		case REG_AON_CPU_MEMFLT_CTL01_EL1:
+		case REG_REDIR_ACNTHP_CTL_EL2:
+		case REG_LCL_CNTVCTSS_NOREDIR_EL0:
+		case REG_AGTCNTP_CTL_NOREDIR_EL0:
+		case REG_PMESR0_EL1:
+		case REG_LD_LATPROF_CMD_EL1:
+		case REG_AON_CPU_MEMFLT_CTL23_EL1:
+		case REG_REDIR_ACNTHV_CVAL_EL2:
+		case REG_AGTCNTV_CVAL_NOREDIR_EL0:
+		case REG_PMESR1_EL1:
+		case REG_PMCR1_EL2:
+		case REG_AON_CPU_MEMFLT_CTL45_EL1:
+		case REG_REDIR_ACNTHV_TVAL_EL2:
+		case REG_CNTKCTL_NOREDIR_EL1:
+		case REG_AGTCNTV_TVAL_NOREDIR_EL0:
+		case REG_OPMAT0_EL1:
+		case REG_PMCR1_EL12:
+		case REG_AON_CPU_MEMFLT_CTL67_EL1:
+		case REG_REDIR_ACNTHV_CTL_EL2:
+		case REG_CNTP_CVAL_NOREDIR_EL0:
+		case REG_AGTCNTV_CTL_NOREDIR_EL0:
+		case REG_OPMAT1_EL1:
+		case REG_PMCR1_GL12:
+		case REG_AON_CPU_MSTALL_CTR0_EL1:
+		case REG_REDIR_ACNTFRQ_EL0:
+		case REG_CNTP_TVAL_NOREDIR_EL0:
+		case REG_LCL_CNTPCT_NOREDIR_EL0:
+		case REG_OPMSK0_EL1:
+		case REG_LD_LATPROF_CTL_EL12:
+		case REG_AON_CPU_MSTALL_CTR1_EL1:
+		case REG_AGTCNTVOFF_EL2:
+		case REG_CNTP_CTL_NOREDIR_EL0:
+		case REG_CNTV_CTL_NOREDIR_EL0:
+		case REG_OPMSK1_EL1:
+		case REG_LD_LATPROF_INF_EL2:
+		case REG_AON_CPU_MSTALL_CTR2_EL1:
+		case REG_REDIR_ACNTP_CVAL_EL0:
+		case REG_CNTV_CVAL_NOREDIR_EL0:
+		case REG_LCL_ACNTPCT_NOREDIR_EL0:
+		case REG_AON_CPU_MSTALL_CTR3_EL1:
+		case REG_REDIR_ACNTP_TVAL_EL0:
+		case REG_CNTV_TVAL_NOREDIR_EL0:
+		case REG_VMSA_HV_LOCK_EL2:
+		case REG_PMSWCTRL_EL1:
+		case REG_PMCR5_EL0:
+		case REG_AON_CPU_MSTALL_CTR4_EL1:
+		case REG_PMCOMPARE0_EL1:
+		case REG_PMCOMPARE1_EL1:
+		case REG_VMSA_NV_LOCK_EL2:
+		case REG_PMSR_EL1:
+		case REG_AON_CPU_MSTALL_CTR5_EL1:
+		case REG_REDIR_ACNTP_CTL_EL0:
+		case REG_PMCOMPARE5_EL1:
+		case REG_PMCOMPARE6_EL1:
+		case REG_PMCOMPARE7_EL1:
+		case REG_PMCR_BVRNG4_EL1:
+		case REG_PM_PMI_PC:
+		case REG_AON_CPU_MSTALL_CTR6_EL1:
+		case REG_REDIR_ACNTV_CVAL_EL0:
+		case REG_LCL_ACNTVCT_NOREDIR_EL0:
+		case REG_PMCR_BVRNG5_EL1:
+		case REG_AON_CPU_MSTALL_CTR7_EL1:
+		case REG_REDIR_ACNTV_TVAL_EL0:
+		case REG_LCL_ACNTPCTSS_NOREDIR_EL0:
+		case REG_CSSELR_EL1:
+		case REG_PMC0:
+		case REG_UPMCFILTER0:
+		case REG_UPMCFILTER1:
+		case REG_UPMCFILTER2:
+		case REG_UPMCFILTER3:
+		case REG_UPMCFILTER4:
+		case REG_UPMCFILTER5:
+		case REG_UPMCFILTER6:
+		case REG_PMC1:
+		case REG_UPMCFILTER7:
+		case REG_PMC2:
+		case REG_PMC3:
+		case REG_PMC4:
+		case REG_PMC5:
+		case REG_PMC6:
+		case REG_PMC7:
+		case REG_PMC8:
+		case REG_PMC9:
+		case REG_PMTRHLD6_EL1:
+		case REG_PMTRHLD4_EL1:
+		case REG_PMTRHLD2_EL1:
+		case REG_PMMMAP_EL1:
+		case REG_CTR_EL0:
+		case REG_DCZID_EL0:
+		case REG_NZCV:
+		case REG_DAIF:
+		case REG_SVCR:
+		case REG_DIT:
+		case REG_SSBS:
+		case REG_TCO:
+		case REG_FPCR:
+		case REG_FPSR:
+		case REG_DSPSR_EL0:
+		case REG_DLR_EL0:
+		case REG_PMCR_EL0:
+		case REG_PMCNTENSET_EL0:
+		case REG_PMCNTENCLR_EL0:
+		case REG_PMOVSCLR_EL0:
+		case REG_PMSWINC_EL0:
+		case REG_PMSELR_EL0:
+		case REG_PMCCNTR_EL0:
+		case REG_PMXEVTYPER_EL0:
+		case REG_PMXEVCNTR_EL0:
+		case REG_DAIFCLR:
+		case REG_PMUSERENR_EL0:
+		case REG_PMOVSSET_EL0:
+		case REG_TPIDR_EL0:
+		case REG_TPIDRRO_EL0:
+		case REG_TPIDR2_EL0:
+		case REG_SCXTNUM_EL0:
+		case REG_AMCR_EL0:
+		case REG_AMUSERENR_EL0:
+		case REG_AMCNTENCLR0_EL0:
+		case REG_AMCNTENSET0_EL0:
+		case REG_AMCNTENCLR1_EL0:
+		case REG_AMCNTENSET1_EL0:
+		case REG_AMEVCNTR00_EL0:
+		case REG_AMEVCNTR01_EL0:
+		case REG_AMEVCNTR02_EL0:
+		case REG_AMEVCNTR03_EL0:
+		case REG_AMEVCNTR10_EL0:
+		case REG_AMEVCNTR11_EL0:
+		case REG_AMEVCNTR12_EL0:
+		case REG_AMEVCNTR13_EL0:
+		case REG_AMEVCNTR14_EL0:
+		case REG_AMEVCNTR15_EL0:
+		case REG_AMEVCNTR16_EL0:
+		case REG_AMEVCNTR17_EL0:
+		case REG_AMEVCNTR18_EL0:
+		case REG_AMEVCNTR19_EL0:
+		case REG_AMEVCNTR110_EL0:
+		case REG_AMEVCNTR111_EL0:
+		case REG_AMEVCNTR112_EL0:
+		case REG_AMEVCNTR113_EL0:
+		case REG_AMEVCNTR114_EL0:
+		case REG_AMEVCNTR115_EL0:
+		case REG_AMEVTYPER10_EL0:
+		case REG_AMEVTYPER11_EL0:
+		case REG_AMEVTYPER12_EL0:
+		case REG_AMEVTYPER13_EL0:
+		case REG_AMEVTYPER14_EL0:
+		case REG_AMEVTYPER15_EL0:
+		case REG_AMEVTYPER16_EL0:
+		case REG_AMEVTYPER17_EL0:
+		case REG_AMEVTYPER18_EL0:
+		case REG_AMEVTYPER19_EL0:
+		case REG_AMEVTYPER110_EL0:
+		case REG_AMEVTYPER111_EL0:
+		case REG_AMEVTYPER112_EL0:
+		case REG_AMEVTYPER113_EL0:
+		case REG_AMEVTYPER114_EL0:
+		case REG_AMEVTYPER115_EL0:
+		case REG_REDIR_CNTFRQ_EL0:
+		case REG_REDIR_LCL_CNTPCT_EL0:
+		case REG_REDIR_LCL_CNTVCT_EL0:
+		case REG_REDIR_LCL_CNTPCTSS_EL0:
+		case REG_REDIR_LCL_CNTVCTSS_EL0:
+		case REG_REDIR_CNTP_TVAL_EL0:
+		case REG_REDIR_CNTP_CTL_EL0:
+		case REG_REDIR_CNTP_CVAL_EL0:
+		case REG_REDIR_CNTV_TVAL_EL0:
+		case REG_REDIR_CNTV_CTL_EL0:
+		case REG_REDIR_CNTV_CVAL_EL0:
+		case REG_PMEVCNTR0_EL0:
+		case REG_PMEVCNTR1_EL0:
+		case REG_PMEVCNTR2_EL0:
+		case REG_PMEVCNTR3_EL0:
+		case REG_PMEVCNTR4_EL0:
+		case REG_PMEVCNTR5_EL0:
+		case REG_PMEVCNTR6_EL0:
+		case REG_PMEVCNTR7_EL0:
+		case REG_PMEVCNTR8_EL0:
+		case REG_PMEVCNTR9_EL0:
+		case REG_PMEVCNTR10_EL0:
+		case REG_PMEVCNTR11_EL0:
+		case REG_PMEVCNTR12_EL0:
+		case REG_PMEVCNTR13_EL0:
+		case REG_PMEVCNTR14_EL0:
+		case REG_PMEVCNTR15_EL0:
+		case REG_PMEVCNTR16_EL0:
+		case REG_PMEVCNTR17_EL0:
+		case REG_PMEVCNTR18_EL0:
+		case REG_PMEVCNTR19_EL0:
+		case REG_PMEVCNTR20_EL0:
+		case REG_PMEVCNTR21_EL0:
+		case REG_PMEVCNTR22_EL0:
+		case REG_PMEVCNTR23_EL0:
+		case REG_PMEVCNTR24_EL0:
+		case REG_PMEVCNTR25_EL0:
+		case REG_PMEVCNTR26_EL0:
+		case REG_PMEVCNTR27_EL0:
+		case REG_PMEVCNTR28_EL0:
+		case REG_PMEVCNTR29_EL0:
+		case REG_PMEVCNTR30_EL0:
+		case REG_PMEVTYPER0_EL0:
+		case REG_PMEVTYPER1_EL0:
+		case REG_PMEVTYPER2_EL0:
+		case REG_PMEVTYPER3_EL0:
+		case REG_PMEVTYPER4_EL0:
+		case REG_PMEVTYPER5_EL0:
+		case REG_PMEVTYPER6_EL0:
+		case REG_PMEVTYPER7_EL0:
+		case REG_PMEVTYPER8_EL0:
+		case REG_PMEVTYPER9_EL0:
+		case REG_PMEVTYPER10_EL0:
+		case REG_PMEVTYPER11_EL0:
+		case REG_PMEVTYPER12_EL0:
+		case REG_PMEVTYPER13_EL0:
+		case REG_PMEVTYPER14_EL0:
+		case REG_PMEVTYPER15_EL0:
+		case REG_PMEVTYPER16_EL0:
+		case REG_PMEVTYPER17_EL0:
+		case REG_PMEVTYPER18_EL0:
+		case REG_PMEVTYPER19_EL0:
+		case REG_PMEVTYPER20_EL0:
+		case REG_PMEVTYPER21_EL0:
+		case REG_PMEVTYPER22_EL0:
+		case REG_PMEVTYPER23_EL0:
+		case REG_PMEVTYPER24_EL0:
+		case REG_PMEVTYPER25_EL0:
+		case REG_PMEVTYPER26_EL0:
+		case REG_PMEVTYPER27_EL0:
+		case REG_PMEVTYPER28_EL0:
+		case REG_PMEVTYPER29_EL0:
+		case REG_PMEVTYPER30_EL0:
+		case REG_PMCCFILTR_EL0:
+		case REG_LSU_ERR_STS:
+		case REG_AFLATCTL1_EL1:
+		case REG_AFLATVALBIN0_EL1:
+		case REG_AFLATINFLO_EL1:
+		case REG_LSU_ERR_CTL:
+		case REG_AFLATCTL2_EL1:
+		case REG_AFLATVALBIN1_EL1:
+		case REG_AFLATINFHI_EL1:
+		case REG_AFLATCTL3_EL1:
+		case REG_AFLATVALBIN2_EL1:
+		case REG_AFLATCTL4_EL1:
+		case REG_AFLATVALBIN3_EL1:
+		case REG_LLC_FILL_CTL:
+		case REG_AFLATCTL5_LO_EL1:
+		case REG_AFLATVALBIN4_EL1:
+		case REG_AFLATCTL5_HI_EL1:
+		case REG_LLC_FILL_DAT:
+		case REG_AFLATVALBIN5_EL1:
+		case REG_AFLATVALBIN6_EL1:
+		case REG_LLC_RAM_CONFIG:
+		case REG_AFLATVALBIN7_EL1:
+		case REG_LLC_ERR_STS:
+		case REG_CMAINT_BCAST_LIST_0:
+		case REG_CMAINT_BCAST_LIST_1:
+		case REG_CMAINT_BCAST_CTL:
+		case REG_LLC_ERR_ADR:
+		case REG_LLC_ERR_CTL:
+		case REG_LLC_ERR_INJ:
+		case REG_LLC_ERR_INF:
+		case REG_USERTAGSEL_EL1:
+		case REG_UUSERTAG_EL0:
+		case REG_KUSERTAG_EL1:
+		case REG_HUSERTAG_EL2:
+		case REG_LLC_TRACE_CTL0:
+		case REG_LLC_TRACE_CTL1:
+		case REG_LLC_UP_REQ_VC:
+		case REG_LLC_UP_REQ_VC_THRESH:
+		case REG_LLC_UP_REQ_VC_2:
+		case REG_LLC_UP_REQ_VC_THRESH_2:
+		case REG_LLC_DRAM_HASH0:
+		case REG_LLC_DRAM_HASH1:
+		case REG_LLC_DRAM_HASH2:
+		case REG_LLC_DRAM_HASH3:
+		case REG_LLC_TRACE_CTL2:
+		case REG_LLC_DRAM_HASH4:
+		case REG_LLC_UP_REQ_VC_3:
+		case REG_LLC_UP_REQ_VC_THRESH_3:
+		case REG_LLC_UP_REQ_VC_4:
+		case REG_LLC_UP_REQ_VC_THRESH_4:
+		case REG_LLC_HASH0:
+		case REG_LLC_HASH1:
+		case REG_LLC_HASH2:
+		case REG_LLC_HASH3:
+		case REG_LLC_WRR:
+		case REG_LLC_DRAM_HASH5:
+		case REG_LLC_DRAM_HASH6:
+		case REG_VPIDR_EL2:
+		case REG_VMPIDR_EL2:
+		case REG_SCTLR_EL2:
+		case REG_ACTLR_EL2:
+		case REG_HCR_EL2:
+		case REG_MDCR_EL2:
+		case REG_CPTR_EL2:
+		case REG_HSTR_EL2:
+		case REG_HFGRTR_EL2:
+		case REG_HFGWTR_EL2:
+		case REG_HFGITR_EL2:
+		case REG_HACR_EL2:
+		case REG_TRFCR_EL2:
+		case REG_HCRX_EL2:
+		case REG_SMPRIMAP_EL2:
+		case REG_SMCR_EL2:
+		case REG_SDER32_EL2:
+		case REG_TTBR0_EL2:
+		case REG_TTBR1_EL2:
+		case REG_TCR_EL2:
+		case REG_VTTBR_EL2:
+		case REG_VTCR_EL2:
+		case REG_VNCR_EL2:
+		case REG_VSTTBR_EL2:
+		case REG_VSTCR_EL2:
+		case REG_DACR32_EL2:
+		case REG_HDFGRTR_EL2:
+		case REG_HDFGWTR_EL2:
+		case REG_SPSR_NV_EL21:
+		case REG_ELR_NV_EL21:
+		case REG_SP_EL1:
+		case REG_SPSR_IRQ:
+		case REG_SPSR_ABT:
+		case REG_SPSR_UND:
+		case REG_SPSR_FIQ:
+		case REG_IFSR32_EL2:
+		case REG_AFSR0_EL2:
+		case REG_AFSR1_EL2:
+		case REG_ESR_NV_EL21:
+		case REG_VSESR_EL2:
+		case REG_FPEXC32_EL2:
+		case REG_TFSR_EL2:
+		case REG_FAR_NV_EL21:
+		case REG_HPFAR_EL2:
+		case REG_PMSCR_EL2:
+		case REG_MAIR_EL2:
+		case REG_AMAIR_EL2:
+		case REG_MPAMHCR_EL2:
+		case REG_MPAMVPMV_EL2:
+		case REG_MPAM2_EL2:
+		case REG_MPAMVPM0_EL2:
+		case REG_MPAMVPM1_EL2:
+		case REG_MPAMVPM2_EL2:
+		case REG_MPAMVPM3_EL2:
+		case REG_MPAMVPM4_EL2:
+		case REG_MPAMVPM5_EL2:
+		case REG_MPAMVPM6_EL2:
+		case REG_MPAMVPM7_EL2:
+		case REG_VBAR_EL2:
+		case REG_RVBAR_EL2:
+		case REG_RMR_EL2:
+		case REG_VDISR_EL2:
+		case REG_ICH_AP0R0_EL2:
+		case REG_ICH_AP0R1_EL2:
+		case REG_ICH_AP0R2_EL2:
+		case REG_ICH_AP0R3_EL2:
+		case REG_ICH_AP1R0_EL2:
+		case REG_ICH_AP1R1_EL2:
+		case REG_ICH_AP1R2_EL2:
+		case REG_ICH_AP1R3_EL2:
+		case REG_ICH_VSEIR_EL2:
+		case REG_ICC_SRE_EL2:
+		case REG_ICH_HCR_EL2:
+		case REG_ICH_VTR_EL2:
+		case REG_ICH_MISR_EL2:
+		case REG_ICH_EISR_EL2:
+		case REG_ICH_ELRSR_EL2:
+		case REG_ICH_VMCR_EL2:
+		case REG_ICH_LR0_EL2:
+		case REG_ICH_LR1_EL2:
+		case REG_ICH_LR2_EL2:
+		case REG_ICH_LR3_EL2:
+		case REG_ICH_LR4_EL2:
+		case REG_ICH_LR5_EL2:
+		case REG_ICH_LR6_EL2:
+		case REG_ICH_LR7_EL2:
+		case REG_ICH_LR8_EL2:
+		case REG_ICH_LR9_EL2:
+		case REG_ICH_LR10_EL2:
+		case REG_ICH_LR11_EL2:
+		case REG_ICH_LR12_EL2:
+		case REG_ICH_LR13_EL2:
+		case REG_ICH_LR14_EL2:
+		case REG_ICH_LR15_EL2:
+		case REG_CONTEXTIDR_EL2:
+		case REG_TPIDR_EL2:
+		case REG_SCXTNUM_EL2:
+		case REG_CNTVOFF_EL2:
+		case REG_REDIR_CNTHCTL_EL2:
+		case REG_REDIR_CNTHP_TVAL_EL2:
+		case REG_REDIR_CNTHP_CTL_EL2:
+		case REG_REDIR_CNTHP_CVAL_EL2:
+		case REG_REDIR_CNTHV_TVAL_EL2:
+		case REG_REDIR_CNTHV_CTL_EL2:
+		case REG_REDIR_CNTHV_CVAL_EL2:
+		case REG_CNTHVS_TVAL_EL2:
+		case REG_CNTHVS_CTL_EL2:
+		case REG_CNTHVS_CVAL_EL2:
+		case REG_CNTHPS_TVAL_EL2:
+		case REG_CNTHPS_CTL_EL2:
+		case REG_CNTHPS_CVAL_EL2:
+		case REG_FED_ERR_STS:
+		case REG_FED_ERR_CTL:
+		case REG_APCTL_EL21:
+		case REG_KERNKEYLO_EL21:
+		case REG_KERNKEYHI_EL21:
+		case REG_VMSA_LOCK_EL1:
+		case REG_AMX_STATE_T_EL1:
+		case REG_AMX_CONFIG_EL21:
+		case REG_VMSA_LOCK_EL2:
+		case REG_CTRR_B_UPR_EL21:
+		case REG_CTRR_B_LWR_EL21:
+		case REG_SP_SETUP_GL21:
+		case REG_SP_SETUP_GL2:
+		case REG_CTRR_B_CTL_EL21:
+		case REG_CTRR_A_LWR_EL21:
+		case REG_CTRR_A_UPR_EL21:
+		case REG_CTRR_A_CTL_EL21:
+		case REG_VMSA_LOCK_EL12:
+		case REG_AGTCNTV_CTL_EL02:
+		case REG_AMX_STATE_EL1:
+		case REG_AMX_STATUS_EL1:
+		case REG_AGTCNTP_CVAL_EL02:
+		case REG_REDIR_ACNTP_TVAL_EL02:
+		case REG_AGTCNTP_CTL_EL02:
+		case REG_AGTCNTV_CVAL_EL02:
+		case REG_AGTCNTV_TVAL_EL02:
+		case REG_AMX_CONFIG_EL12:
+		case REG_AMX_CONFIG_EL2:
+		case REG_SPRR_HUPERM_EL0:
+		case REG_SPRR_VUPERM_EL0:
+		case REG_CTRR_A_CTL_EL2:
+		case REG_CTRR_B_CTL_EL2:
+		case REG_CTRR_A_LWR_EL2:
+		case REG_CTRR_A_UPR_EL2:
+		case REG_CTRR_B_LWR_EL2:
+		case REG_CTRR_B_UPR_EL2:
+		case REG_SPRR_HUMPRR_EL2:
+		case REG_SPRR_HUPERM_SH01_EL2:
+		case REG_SPRR_HUPERM_SH02_EL2:
+		case REG_SPRR_HUPERM_SH03_EL2:
+		case REG_SPRR_HUPERM_SH04_EL2:
+		case REG_SPRR_HUPERM_SH05_EL2:
+		case REG_SPRR_HUPERM_SH06_EL2:
+		case REG_SPRR_HUPERM_SH07_EL2:
+		case REG_SPRR_VUMPRR_EL1:
+		case REG_SPRR_VUPERM_SH01_EL1:
+		case REG_SPRR_VUPERM_SH02_EL1:
+		case REG_SPRR_VUPERM_SH03_EL1:
+		case REG_SPRR_VUPERM_SH04_EL1:
+		case REG_SPRR_VUPERM_SH05_EL1:
+		case REG_SPRR_VUPERM_SH06_EL1:
+		case REG_SPRR_VUPERM_SH07_EL1:
+		case REG_CTRR_A_LWR_EL12:
+		case REG_CTRR_A_UPR_EL12:
+		case REG_CTRR_B_LWR_EL12:
+		case REG_CTRR_B_UPR_EL12:
+		case REG_CTRR_A_CTL_EL12:
+		case REG_CTRR_B_CTL_EL12:
+		case REG_REDIR_ACNTKCTL_EL1:
+		case REG_AGTCNTKCTL_EL12:
+		case REG_PREDAKEYLO_EL1:
+		case REG_PREDAKEYHI_EL1:
+		case REG_PREDBKEYLO_EL1:
+		case REG_PREDBKEYHI_EL1:
+		case REG_SIQ_CFG_EL1:
+		case REG_REDIR_LCL_ACNTPCTSS_EL0:
+		case REG_REDIR_LCL_ACNTVCTSS_EL0:
+		case REG_AVNCR_EL2:
+		case REG_ACC_CTRR_A_LWR_EL2:
+		case REG_ACC_CTRR_A_UPR_EL2:
+		case REG_ACC_CTRR_B_LWR_EL2:
+		case REG_ACC_CTRR_B_UPR_EL2:
+		case REG_ACC_CTRR_A_CTL_EL2:
+		case REG_ACC_CTRR_B_CTL_EL2:
+		case REG_REDIR_LCL_ACNTPCT_EL0:
+		case REG_REDIR_LCL_ACNTVCT_EL0:
+		case REG_ACFG_EL1:
+		case REG_AHCR_EL2:
+		case REG_APL_INTSTATUS_EL21:
+		case REG_APL_INTSTATUS_EL2:
+		case REG_REDIR_ACNTHCTL_EL2:
+		case REG_JAPIAKEYLO_NV_EL21:
+		case REG_JAPIAKEYHI_NV_EL21:
+		case REG_JAPIBKEYLO_NV_EL21:
+		case REG_JAPIBKEYHI_NV_EL21:
+		case REG_JAPIAKEYLO_EL21:
+		case REG_JAPIAKEYHI_EL21:
+		case REG_JAPIBKEYLO_EL21:
+		case REG_JAPIBKEYHI_EL21:
+		case REG_JAPIAKEYLO_EL12:
+		case REG_JAPIAKEYHI_EL12:
+		case REG_JAPIBKEYLO_EL12:
+		case REG_JAPIBKEYHI_EL12:
+		case REG_AGTCNTRDIR_EL2:
+		case REG_AGTCNTRDIR_EL12:
+		case REG_JRANGE_EL2:
+		case REG_JRANGE_EL21:
+		case REG_JRANGE_EL12:
+		case REG_JCTL_EL2:
+		case REG_JCTL_EL21:
+		case REG_JCTL_EL12:
+		case REG_JCTL_EL0:
+		case REG_AMDSCR_EL1:
+		case REG_SCTLR_EL12:
+		case REG_ACTLR_EL12:
+		case REG_CPACR_EL12:
+		case REG_TRFCR_EL12:
+		case REG_SMCR_EL12:
+		case REG_TTBR0_EL12:
+		case REG_TTBR1_EL12:
+		case REG_TCR_EL12:
+		case REG_SPSR_EL12:
+		case REG_ELR_EL12:
+		case REG_AFSR0_EL12:
+		case REG_AFSR1_EL12:
+		case REG_ESR_EL12:
+		case REG_TFSR_EL12:
+		case REG_FAR_EL12:
+		case REG_PMSCR_EL12:
+		case REG_MAIR_EL12:
+		case REG_AMAIR_EL12:
+		case REG_MPAM1_EL12:
+		case REG_VBAR_EL12:
+		case REG_CONTEXTIDR_EL12:
+		case REG_SCXTNUM_EL12:
+		case REG_CNTKCTL_EL12:
+		case REG_CNTP_TVAL_EL02:
+		case REG_CNTP_CTL_EL02:
+		case REG_CNTP_CVAL_EL02:
+		case REG_CNTV_TVAL_EL02:
+		case REG_CNTV_CTL_EL02:
+		case REG_CNTV_CVAL_EL02:
+		case REG_IPI_RR_LOCAL_EL1:
+		case REG_IPI_RR_GLOBAL_EL1:
+		case REG_AF_ERR_CFG0:
+		case REG_AP_ERR_CFG0:
+		case REG_AF_ERR_SRC_IDS:
+		case REG_DPC_ERR_STS:
+		case REG_DPC_ERR_CTL:
+		case REG_PROD_TRC_CORE_CFG_EL21:
+		case REG_TRACE_CORE_CFG:
+		case REG_IPI_SR:
+		case REG_APL_LRTMR_EL2:
+		case REG_APL_INTENABLE_EL2:
+		case REG_KTRACE_MESSAGE:
+		case REG_TRACE_CORE_CFG_EXT:
+		case REG_PROD_TRC_CORE_CFG_EL2:
+		case REG_HID_PROD_TRC_CORE_CFG_EL1:
+		case REG_DBG_WRAP_GLB:
+		case REG_TRACE_STREAM_BASE:
+		case REG_TRACE_STREAM_FILL:
+		case REG_TRACE_STREAM_BASE1:
+		case REG_TRACE_STREAM_FILL1:
+		case REG_TRACE_STREAM_IRQ:
+		case REG_WATCHDOGDIAG0:
+		case REG_WATCHDOGDIAG1:
+		case REG_TRACE_AUX_CTL:
+		case REG_IPI_CR:
+		case REG_UTRIG_EVENT:
+		case REG_HID_PROD_TRC_MASK_EL1:
+		case REG_TRACE_CTL:
+		case REG_TRACE_DAT:
+		case REG_PROD_TRC_STRM_BASE0_GL2:
+		case REG_PROD_TRC_STRM_BASE1_GL2:
+		case REG_CPU_CFG:
+		case REG_PBLK_STS:
+		case REG_PROD_TRC_CTL_EL21:
+		case REG_PROD_TRC_STRM_BASE0_GL21:
+		case REG_PROD_TRC_STRM_BASE1_GL21:
+		case REG_PROD_TRC_STRM_FIQ_EL21:
+		case REG_CPU_OVRD:
+		case REG_PBLK_EXE_ST:
+		case REG_PROD_TRC_CORE_GL_CTL_GL21:
+		case REG_PROD_TRC_CORE_GL_CTL_GL2:
+		case REG_ACC_OVRD:
+		case REG_ACC_OVRD1:
+		case REG_CPM_PWRDN_CTL:
+		case REG_PROD_TRC_BUF_RESTORE0_GL21:
+		case REG_PROD_TRC_BUF_RESTORE1_GL21:
+		case REG_PROD_TRC_EN_GL21:
+		case REG_PRE_LLCFLUSH_TMR:
+		case REG_BIUINTFCTL_CFG:
+		case REG_BIUINTFWRR_CFG:
+		case REG_PRE_TD_TMR:
+		case REG_ACC_SLP_WAKE_UP_TMR:
+		case REG_PBLK_PSW_DLY:
+		case REG_CPU_STS:
+		case REG_HIST_TRIG:
+		case REG_PROD_TRC_BUF_RESTORE0_GL2:
+		case REG_PROD_TRC_BUF_RESTORE1_GL2:
+		case REG_PROD_TRC_STRM_FILL0_EL1:
+		case REG_PROD_TRC_STRM_FILL1_EL1:
+		case REG_ARRAY_INDEX:
+		case REG_PROD_TRC_CTL_EL2:
+		case REG_PROD_TRC_EN_GL2:
+		case REG_PROD_TRC_STRM_FIQ_EL2:
+		case REG_PROD_TRC_CPMU_DUMP_TRIG_EL1:
+		case REG_PROD_LOSS_COUNT_EL1:
+		case REG_SW_TRACE_DATA_EL0:
+		case REG_IL1_DATA0:
+		case REG_IL1_DATA1:
+		case REG_DL1_DATA0:
+		case REG_DL1_DATA1:
+		case REG_MMUDATA0:
+		case REG_MMUDATA1:
+		case REG_DL1_DATA2:
+		case REG_IL1_DATA2:
+		case REG_LLC_DATA0:
+		case REG_LLC_DATA1:
+		case REG_SCTLR_EL3:
+		case REG_ACTLR_EL3:
+		case REG_SCR_EL3:
+		case REG_SDER32_EL3:
+		case REG_CPTR_EL3:
+		case REG_MDCR_EL3:
+		case REG_TTBR0_EL3:
+		case REG_TCR_EL3:
+		case REG_SPSR_EL3:
+		case REG_ELR_EL3:
+		case REG_SP_EL2:
+		case REG_AFSR0_EL3:
+		case REG_AFSR1_EL3:
+		case REG_ESR_EL3:
+		case REG_TFSR_EL3:
+		case REG_FAR_EL3:
+		case REG_MAIR_EL3:
+		case REG_AMAIR_EL3:
+		case REG_MPAM3_EL3:
+		case REG_VBAR_EL3:
+		case REG_RVBAR_EL3:
+		case REG_RMR_EL3:
+		case REG_ICC_CTLR_EL3:
+		case REG_ICC_SRE_EL3:
+		case REG_ICC_IGRPEN1_EL3:
+		case REG_TPIDR_EL3:
+		case REG_SCXTNUM_EL3:
+		case REG_MMU_ERR_STS:
+		case REG_AFSR1_GL21:
+		case REG_AFSR1_GL2:
+		case REG_AFSR1_GL12:
+		case REG_BP_OBJC_ADR_EL1:
+		case REG_BP_OBJC_CTL_EL1:
+		case REG_SP_GL11_GL21:
+		case REG_MMU_SESR_EL2:
+		case REG_SPRR_CONFIG_EL21:
+		case REG_HPFAR_GL2:
+		case REG_GXF_CONFIG_EL21:
+		case REG_SPRR_AMRANGE_EL1:
+		case REG_GXF_CONFIG_EL2:
+		case REG_SPRR_UPERM_EL02:
+		case REG_SPRR_PPERM_EL21:
+		case REG_SPRR_PPERM_EL2:
+		case REG_APGAKEYLO_EL12:
+		case REG_APGAKEYHI_EL12:
+		case REG_KERNKEYLO_EL12:
+		case REG_KERNKEYHI_EL12:
+		case REG_AFPCR_EL0:
+		case REG_SP_GL22:
+		case REG_AMXIDR_EL1:
+		case REG_SPRR_UMPRR_EL1:
+		case REG_SPRR_PMPRR_EL21:
+		case REG_SPRR_PMPRR_EL2:
+		case REG_SPRR_UPERM_SH01_EL1:
+		case REG_SPRR_UPERM_SH02_EL1:
+		case REG_SPRR_UPERM_SH03_EL1:
+		case REG_SPRR_UPERM_SH04_EL1:
+		case REG_SPRR_UPERM_SH05_EL1:
+		case REG_SPRR_UPERM_SH06_EL1:
+		case REG_SPRR_UPERM_SH07_EL1:
+		case REG_SPRR_PPERM_SH01_EL21:
+		case REG_SPRR_PPERM_SH02_EL21:
+		case REG_SPRR_PPERM_SH03_EL21:
+		case REG_SPRR_PPERM_SH04_EL21:
+		case REG_SPRR_PPERM_SH05_EL21:
+		case REG_SPRR_PPERM_SH06_EL21:
+		case REG_SPRR_PPERM_SH07_EL21:
+		case REG_SPRR_PPERM_SH01_EL2:
+		case REG_SPRR_PPERM_SH02_EL2:
+		case REG_SPRR_PPERM_SH03_EL2:
+		case REG_SPRR_PPERM_SH04_EL2:
+		case REG_SPRR_PPERM_SH05_EL2:
+		case REG_SPRR_PPERM_SH06_EL2:
+		case REG_SPRR_PPERM_SH07_EL2:
+		case REG_SPRR_PMPRR_EL12:
+		case REG_SPRR_PPERM_SH01_EL12:
+		case REG_SPRR_PPERM_SH02_EL12:
+		case REG_SPRR_PPERM_SH03_EL12:
+		case REG_SPRR_PPERM_SH04_EL12:
+		case REG_SPRR_PPERM_SH05_EL12:
+		case REG_SPRR_PPERM_SH06_EL12:
+		case REG_SPRR_PPERM_SH07_EL12:
+		case REG_APIAKEYLO_EL12:
+		case REG_APIAKEYHI_EL12:
+		case REG_APIBKEYLO_EL12:
+		case REG_APIBKEYHI_EL12:
+		case REG_APDAKEYLO_EL12:
+		case REG_APDAKEYHI_EL12:
+		case REG_APDBKEYLO_EL12:
+		case REG_APDBKEYHI_EL12:
+		case REG_CURRENTG:
+		case REG_GXF_ENTRY_EL21:
+		case REG_GXF_PABENTRY_EL21:
+		case REG_ASPSR_EL21:
+		case REG_ADSPSR_EL0:
+		case REG_PMCR1_GL2:
+		case REG_ASPSR_NV_EL21:
+		case REG_PMCR1_GL21:
+		case REG_VBAR_GL12:
+		case REG_SPSR_GL12:
+		case REG_ASPSR_GL12:
+		case REG_ESR_GL12:
+		case REG_ELR_GL12:
+		case REG_FAR_GL12:
+		case REG_SP_GL1:
+		case REG_TPIDR_GL1:
+		case REG_VBAR_GL21:
+		case REG_SPSR_GL21:
+		case REG_ASPSR_GL21:
+		case REG_ESR_GL21:
+		case REG_ELR_GL21:
+		case REG_FAR_GL21:
+		case REG_SP_GL2:
+		case REG_TPIDR_GL2:
+		case REG_VBAR_GL2:
+		case REG_SPSR_GL2:
+		case REG_ASPSR_GL2:
+		case REG_ESR_GL2:
+		case REG_ELR_GL2:
+		case REG_FAR_GL2:
+		case REG_GXF_ENTRY_EL2:
+		case REG_GXF_PABENTRY_EL2:
+		case REG_APCTL_EL2:
+		case REG_APSTS_EL2:
+		case REG_APSTS_NV1_EL1:
+		case REG_KERNKEYLO_NV_EL21:
+		case REG_KERNKEYHI_NV_EL21:
+		case REG_ASPSR_EL12:
+		case REG_APIAKEYLO_NV_EL21:
+		case REG_APIAKEYHI_NV_EL21:
+		case REG_APIBKEYLO_NV_EL21:
+		case REG_APIBKEYHI_NV_EL21:
+		case REG_APDAKEYLO_NV_EL21:
+		case REG_APDAKEYHI_NV_EL21:
+		case REG_APDBKEYLO_NV_EL21:
+		case REG_APDBKEYHI_NV_EL21:
+		case REG_APGAKEYLO_NV_EL21:
+		case REG_APGAKEYHI_NV_EL21:
+		case REG_SPRR_CONFIG_EL2:
+		case REG_SPRR_AMRANGE_EL2:
+		case REG_VMKEYLO_EL2:
+		case REG_VMKEYHI_EL2:
+		case REG_MMU_SFAR_EL2:
+		case REG_APSTS_EL12:
+		case REG_APCTL_EL12:
+		case REG_GXF_CONFIG_EL12:
+		case REG_GXF_ENTRY_EL12:
+		case REG_GXF_PABENTRY_EL12:
+		case REG_SPRR_CONFIG_EL12:
+		case REG_SPRR_AMRANGE_EL12:
+		case REG_MMU_SESR_CTL_EL2:
+		case REG_SPRR_PPERM_EL12:
+		case REG_CNTPS_TVAL_EL1:
+		case REG_CNTPS_CTL_EL1:
+		case REG_CNTPS_CVAL_EL1:
+		case REG_PSTATE_SPSEL:
+		case REG_PWRDNSAVE0:
+		case REG_NRG_ACC_CTL:
+		case REG_AON_CNT0:
+		case REG_CPU_CNT0:
+		case REG_UPMCR0_EL1:
+		case REG_UPMC8:
+		case REG_AON_CNT8:
+		case REG_PWRDNSAVE1:
+		case REG_CORE_NRG_ACC_DAT:
+		case REG_AON_CNT_CTL0:
+		case REG_CPU_CNT_CTL0:
+		case REG_UPMESR0_EL1:
+		case REG_UPMC9:
+		case REG_AON_CNT_CTL8:
+		case REG_ACC_PWR_DN_SAVE:
+		case REG_CPM_NRG_ACC_DAT:
+		case REG_AON_CNT1:
+		case REG_CPU_CNT1:
+		case REG_UPMSWCTRL_EL1:
+		case REG_UPMC10:
+		case REG_AON_CNT9:
+		case REG_CORE_SRM_NRG_ACC_DAT:
+		case REG_AON_CNT_CTL1:
+		case REG_CPU_CNT_CTL1:
+		case REG_UPMECM0_EL1:
+		case REG_UPMC11:
+		case REG_AON_CNT_CTL9:
+		case REG_AON_CNT_CTL:
+		case REG_CPM_SRM_NRG_ACC_DAT:
+		case REG_AON_CNT2:
+		case REG_CPU_CNT2:
+		case REG_UPMECM1_EL1:
+		case REG_UPMC12:
+		case REG_AON_CNT10:
+		case REG_CPU_CNT_CTL:
+		case REG_AON_CNT_CTL2:
+		case REG_CPU_CNT_CTL2:
+		case REG_UPMPCM_EL1:
+		case REG_UPMC13:
+		case REG_AON_CNT_CTL10:
+		case REG_AON_CNT3:
+		case REG_CPU_CNT3:
+		case REG_UPMSR_EL1:
+		case REG_UPMC14:
+		case REG_AON_CNT11:
+		case REG_AON_CNT_CTL3:
+		case REG_CPU_CNT_CTL3:
+		case REG_UPMC0:
+		case REG_UPMC15:
+		case REG_AON_CNT_CTL11:
+		case REG_AON_CNT4:
+		case REG_CPU_CNT4:
+		case REG_UPMC1:
+		case REG_UPMECM2_EL1:
+		case REG_AON_CNT_CTL4:
+		case REG_CPU_CNT_CTL4:
+		case REG_UPMC2:
+		case REG_UPMECM3_EL1:
+		case REG_AON_CNT5:
+		case REG_CPU_CNT5:
+		case REG_UPMC3:
+		case REG_UPMCR1_EL1:
+		case REG_AON_CNT_CTL5:
+		case REG_CPU_CNT_CTL5:
+		case REG_UPMC4:
+		case REG_UPMESR1_EL1:
+		case REG_AON_CNT6:
+		case REG_CPU_CNT6:
+		case REG_UPMC5:
+		case REG_AON_CNT_CTL6:
+		case REG_CPU_CNT_CTL6:
+		case REG_UPMC6:
+		case REG_AON_CNT7:
+		case REG_CPU_CNT7:
+		case REG_UPMC7:
+		case REG_AON_CNT_CTL7:
+		case REG_CPU_CNT_CTL7:
+		return true;
+	default: return false;
+	}
+}
+
+