diff options
| author | Galen Williamson <galen@vector35.com> | 2025-03-25 21:27:51 -0400 |
|---|---|---|
| committer | Galen Williamson <galen@vector35.com> | 2025-03-31 18:31:33 -0400 |
| commit | b095215397ca8fe7e9808f312403ec4494de76f6 (patch) | |
| tree | 5eebe61a44d2f95aa5fadd78d9974234fca376be /arch/arm64/disassembler/sysregs_gen.h | |
| parent | 8093106217331012734564301118244748535715 (diff) | |
[aarch64] Updating Aarch64 system registers to 2024-12 spec, fix MSR/MRS lifting to use ReadMSR/WriteMSR intrinsics that take enums, removing the sysregs from the register list of the architecture
* sysregs are no longer registers, add enum for TLBI and AT operands
* add erroneously missing cases for unsupported encodings, add enum for DC operands
Diffstat (limited to 'arch/arm64/disassembler/sysregs_gen.h')
| -rw-r--r-- | arch/arm64/disassembler/sysregs_gen.h | 1560 |
1 files changed, 1560 insertions, 0 deletions
diff --git a/arch/arm64/disassembler/sysregs_gen.h b/arch/arm64/disassembler/sysregs_gen.h new file mode 100644 index 00000000..b7a16cd5 --- /dev/null +++ b/arch/arm64/disassembler/sysregs_gen.h @@ -0,0 +1,1560 @@ +#pragma once + +#include <stdbool.h> + +enum SystemReg { + SYSREG_NONE=0, + REG_EDSCR =4 /* 4 */, // S0_0_c0_c0_4 at min EL0: EDSCR + REG_EDPRSR =24 /* 24 */, // S0_0_c0_c3_0 at min EL0: EDPRSR + REG_UAOIMM =515 /* 515 */, // S0_0_c4_c0_3 at min EL1: UAOIMM + REG_PANIMM =516 /* 516 */, // S0_0_c4_c0_4 at min EL1: PANIMM + REG_SPSELIMM =517 /* 517 */, // S0_0_c4_c0_5 at min EL1: SPSELIMM + REG_DITIMM =6658 /* 6658 */, // S0_3_c4_c0_2 at min EL1: DITIMM + REG_SVCRIMM =6659 /* 6659 */, // S0_3_c4_c0_3 at min EL1: SVCRIMM + REG_ICIALLUIS =17288 /* 17288 */, // S1_0_c7_c1_0 at min EL1: ICIALLUIS + REG_ICIALLU =17320 /* 17320 */, // S1_0_c7_c5_0 at min EL1: ICIALLU + REG_DCIVAC =17329 /* 17329 */, // S1_0_c7_c6_1 at min EL1: DCIVAC + REG_DCISW =17330 /* 17330 */, // S1_0_c7_c6_2 at min EL1: DCISW + REG_ATS1E1R =17344 /* 17344 */, // S1_0_c7_c8_0 at min EL1: ATS1E1R + REG_ATS1E1W =17345 /* 17345 */, // S1_0_c7_c8_1 at min EL1: ATS1E1W + REG_ATS1E0R =17346 /* 17346 */, // S1_0_c7_c8_2 at min EL1: ATS1E0R + REG_ATS1E0W =17347 /* 17347 */, // S1_0_c7_c8_3 at min EL1: ATS1E0W + REG_DCCSW =17362 /* 17362 */, // S1_0_c7_c10_2 at min EL1: DCCSW + REG_DCCISW =17394 /* 17394 */, // S1_0_c7_c14_2 at min EL1: DCCISW + REG_TLBIVMALLE1IS =17432 /* 17432 */, // S1_0_c8_c3_0 at min EL1: TLBIVMALLE1IS + REG_TLBIVAE1IS =17433 /* 17433 */, // S1_0_c8_c3_1 at min EL1: TLBIVAE1IS + REG_TLBIASIDE1IS =17434 /* 17434 */, // S1_0_c8_c3_2 at min EL1: TLBIASIDE1IS + REG_TLBIVAAE1IS =17435 /* 17435 */, // S1_0_c8_c3_3 at min EL1: TLBIVAAE1IS + REG_TLBIVALE1IS =17437 /* 17437 */, // S1_0_c8_c3_5 at min EL1: TLBIVALE1IS + REG_TLBIVAALE1IS =17439 /* 17439 */, // S1_0_c8_c3_7 at min EL1: TLBIVAALE1IS + REG_TLBIVMALLE1 =17464 /* 17464 */, // S1_0_c8_c7_0 at min EL1: TLBIVMALLE1 + REG_TLBIVAE1 =17465 /* 17465 */, // S1_0_c8_c7_1 at min EL1: TLBIVAE1 + REG_TLBIASIDE1 =17466 /* 17466 */, // S1_0_c8_c7_2 at min EL1: TLBIASIDE1 + REG_TLBIVAAE1 =17467 /* 17467 */, // S1_0_c8_c7_3 at min EL1: TLBIVAAE1 + REG_TLBIVALE1 =17469 /* 17469 */, // S1_0_c8_c7_5 at min EL1: TLBIVALE1 + REG_TLBIVAALE1 =17471 /* 17471 */, // S1_0_c8_c7_7 at min EL1: TLBIVAALE1 + REG_DCZVA =23457 /* 23457 */, // S1_3_c7_c4_1 at min EL1: DCZVA + REG_ICIVAU =23465 /* 23465 */, // S1_3_c7_c5_1 at min EL1: ICIVAU + REG_DCCVAC =23505 /* 23505 */, // S1_3_c7_c10_1 at min EL1: DCCVAC + REG_DCCVAU =23513 /* 23513 */, // S1_3_c7_c11_1 at min EL1: DCCVAU + REG_DCCIVAC =23537 /* 23537 */, // S1_3_c7_c14_1 at min EL1: DCCIVAC + REG_ATS1E2R =25536 /* 25536 */, // S1_4_c7_c8_0 at min EL1: ATS1E2R + REG_ATS1E2W =25537 /* 25537 */, // S1_4_c7_c8_1 at min EL1: ATS1E2W + REG_ATS12E1R =25540 /* 25540 */, // S1_4_c7_c8_4 at min EL1: ATS12E1R + REG_ATS12E1W =25541 /* 25541 */, // S1_4_c7_c8_5 at min EL1: ATS12E1W + REG_ATS12E0R =25542 /* 25542 */, // S1_4_c7_c8_6 at min EL1: ATS12E0R + REG_ATS12E0W =25543 /* 25543 */, // S1_4_c7_c8_7 at min EL1: ATS12E0W + REG_TLBIIPAS2E1IS =25601 /* 25601 */, // S1_4_c8_c0_1 at min EL1: TLBIIPAS2E1IS + REG_TLBIIPAS2LE1IS =25605 /* 25605 */, // S1_4_c8_c0_5 at min EL1: TLBIIPAS2LE1IS + REG_TLBIALLE2IS =25624 /* 25624 */, // S1_4_c8_c3_0 at min EL1: TLBIALLE2IS + REG_TLBIVAE2IS =25625 /* 25625 */, // S1_4_c8_c3_1 at min EL1: TLBIVAE2IS + REG_TLBIALLE1IS =25628 /* 25628 */, // S1_4_c8_c3_4 at min EL1: TLBIALLE1IS + REG_TLBIVALE2IS =25629 /* 25629 */, // S1_4_c8_c3_5 at min EL1: TLBIVALE2IS + REG_TLBIVMALLS12E1IS =25630 /* 25630 */, // S1_4_c8_c3_6 at min EL1: TLBIVMALLS12E1IS + REG_TLBIIPAS2E1 =25633 /* 25633 */, // S1_4_c8_c4_1 at min EL1: TLBIIPAS2E1 + REG_TLBIIPAS2LE1 =25637 /* 25637 */, // S1_4_c8_c4_5 at min EL1: TLBIIPAS2LE1 + REG_TLBIALLE2 =25656 /* 25656 */, // S1_4_c8_c7_0 at min EL1: TLBIALLE2 + REG_TLBIVAE2 =25657 /* 25657 */, // S1_4_c8_c7_1 at min EL1: TLBIVAE2 + REG_TLBIALLE1 =25660 /* 25660 */, // S1_4_c8_c7_4 at min EL1: TLBIALLE1 + REG_TLBIVALE2 =25661 /* 25661 */, // S1_4_c8_c7_5 at min EL1: TLBIVALE2 + REG_TLBIVMALLS12E1 =25662 /* 25662 */, // S1_4_c8_c7_6 at min EL1: TLBIVMALLS12E1 + REG_ATS1E3R =29632 /* 29632 */, // S1_6_c7_c8_0 at min EL1: ATS1E3R + REG_ATS1E3W =29633 /* 29633 */, // S1_6_c7_c8_1 at min EL1: ATS1E3W + REG_TLBIALLE3IS =29720 /* 29720 */, // S1_6_c8_c3_0 at min EL1: TLBIALLE3IS + REG_TLBIVAE3IS =29721 /* 29721 */, // S1_6_c8_c3_1 at min EL1: TLBIVAE3IS + REG_TLBIVALE3IS =29725 /* 29725 */, // S1_6_c8_c3_5 at min EL1: TLBIVALE3IS + REG_TLBIALLE3 =29752 /* 29752 */, // S1_6_c8_c7_0 at min EL1: TLBIALLE3 + REG_TLBIVAE3 =29753 /* 29753 */, // S1_6_c8_c7_1 at min EL1: TLBIVAE3 + REG_TLBIVALE3 =29757 /* 29757 */, // S1_6_c8_c7_5 at min EL1: TLBIVALE3 + REG_OSDTRRX_EL1 =32770 /* 32770 */, // S2_0_c0_c0_2 at min EL1: OSDTRRX_EL1 + REG_DBGBVR0_EL1 =32772 /* 32772 */, // S2_0_c0_c0_4 at min EL1: DBGBVR0_EL1 + REG_DBGBCR0_EL1 =32773 /* 32773 */, // S2_0_c0_c0_5 at min EL1: DBGBCR0_EL1 + REG_DBGWVR0_EL1 =32774 /* 32774 */, // S2_0_c0_c0_6 at min EL1: DBGWVR0_EL1 + REG_DBGWCR0_EL1 =32775 /* 32775 */, // S2_0_c0_c0_7 at min EL1: DBGWCR0_EL1 + REG_DBGBVR1_EL1 =32780 /* 32780 */, // S2_0_c0_c1_4 at min EL1: DBGBVR1_EL1 + REG_DBGBCR1_EL1 =32781 /* 32781 */, // S2_0_c0_c1_5 at min EL1: DBGBCR1_EL1 + REG_DBGWVR1_EL1 =32782 /* 32782 */, // S2_0_c0_c1_6 at min EL1: DBGWVR1_EL1 + REG_DBGWCR1_EL1 =32783 /* 32783 */, // S2_0_c0_c1_7 at min EL1: DBGWCR1_EL1 + REG_MDCCINT_EL1 =32784 /* 32784 */, // S2_0_c0_c2_0 at min EL1: MDCCINT_EL1 + REG_MDSCR_EL1 =32786 /* 32786 */, // S2_0_c0_c2_2 at min EL1: MDSCR_EL1 + REG_DBGBVR2_EL1 =32788 /* 32788 */, // S2_0_c0_c2_4 at min EL1: DBGBVR2_EL1 + REG_DBGBCR2_EL1 =32789 /* 32789 */, // S2_0_c0_c2_5 at min EL1: DBGBCR2_EL1 + REG_DBGWVR2_EL1 =32790 /* 32790 */, // S2_0_c0_c2_6 at min EL1: DBGWVR2_EL1 + REG_DBGWCR2_EL1 =32791 /* 32791 */, // S2_0_c0_c2_7 at min EL1: DBGWCR2_EL1 + REG_OSDTRTX_EL1 =32794 /* 32794 */, // S2_0_c0_c3_2 at min EL1: OSDTRTX_EL1 + REG_DBGBVR3_EL1 =32796 /* 32796 */, // S2_0_c0_c3_4 at min EL1: DBGBVR3_EL1 + REG_DBGBCR3_EL1 =32797 /* 32797 */, // S2_0_c0_c3_5 at min EL1: DBGBCR3_EL1 + REG_DBGWVR3_EL1 =32798 /* 32798 */, // S2_0_c0_c3_6 at min EL1: DBGWVR3_EL1 + REG_DBGWCR3_EL1 =32799 /* 32799 */, // S2_0_c0_c3_7 at min EL1: DBGWCR3_EL1 + REG_DBGBVR4_EL1 =32804 /* 32804 */, // S2_0_c0_c4_4 at min EL1: DBGBVR4_EL1 + REG_DBGBCR4_EL1 =32805 /* 32805 */, // S2_0_c0_c4_5 at min EL1: DBGBCR4_EL1 + REG_DBGWVR4_EL1 =32806 /* 32806 */, // S2_0_c0_c4_6 at min EL1: DBGWVR4_EL1 + REG_DBGWCR4_EL1 =32807 /* 32807 */, // S2_0_c0_c4_7 at min EL1: DBGWCR4_EL1 + REG_DBGBVR5_EL1 =32812 /* 32812 */, // S2_0_c0_c5_4 at min EL1: DBGBVR5_EL1 + REG_DBGBCR5_EL1 =32813 /* 32813 */, // S2_0_c0_c5_5 at min EL1: DBGBCR5_EL1 + REG_DBGWVR5_EL1 =32814 /* 32814 */, // S2_0_c0_c5_6 at min EL1: DBGWVR5_EL1 + REG_DBGWCR5_EL1 =32815 /* 32815 */, // S2_0_c0_c5_7 at min EL1: DBGWCR5_EL1 + REG_DBGWFAR =32816 /* 32816 */, // S2_0_c0_c6_0 at min EL1: DBGWFAR + REG_OSECCR_EL1 =32818 /* 32818 */, // S2_0_c0_c6_2 at min EL1: OSECCR_EL1 + REG_DBGBVR6_EL1 =32820 /* 32820 */, // S2_0_c0_c6_4 at min EL1: DBGBVR6_EL1 + REG_DBGBCR6_EL1 =32821 /* 32821 */, // S2_0_c0_c6_5 at min EL1: DBGBCR6_EL1 + REG_DBGWVR6_EL1 =32822 /* 32822 */, // S2_0_c0_c6_6 at min EL1: DBGWVR6_EL1 + REG_DBGWCR6_EL1 =32823 /* 32823 */, // S2_0_c0_c6_7 at min EL1: DBGWCR6_EL1 + REG_DBGBVR7_EL1 =32828 /* 32828 */, // S2_0_c0_c7_4 at min EL1: DBGBVR7_EL1 + REG_DBGBCR7_EL1 =32829 /* 32829 */, // S2_0_c0_c7_5 at min EL1: DBGBCR7_EL1 + REG_DBGWVR7_EL1 =32830 /* 32830 */, // S2_0_c0_c7_6 at min EL1: DBGWVR7_EL1 + REG_DBGWCR7_EL1 =32831 /* 32831 */, // S2_0_c0_c7_7 at min EL1: DBGWCR7_EL1 + REG_DBGBVR8_EL1 =32836 /* 32836 */, // S2_0_c0_c8_4 at min EL1: DBGBVR8_EL1 + REG_DBGBCR8_EL1 =32837 /* 32837 */, // S2_0_c0_c8_5 at min EL1: DBGBCR8_EL1 + REG_DBGWVR8_EL1 =32838 /* 32838 */, // S2_0_c0_c8_6 at min EL1: DBGWVR8_EL1 + REG_DBGWCR8_EL1 =32839 /* 32839 */, // S2_0_c0_c8_7 at min EL1: DBGWCR8_EL1 + REG_DBGBVR9_EL1 =32844 /* 32844 */, // S2_0_c0_c9_4 at min EL1: DBGBVR9_EL1 + REG_DBGBCR9_EL1 =32845 /* 32845 */, // S2_0_c0_c9_5 at min EL1: DBGBCR9_EL1 + REG_DBGWVR9_EL1 =32846 /* 32846 */, // S2_0_c0_c9_6 at min EL1: DBGWVR9_EL1 + REG_DBGWCR9_EL1 =32847 /* 32847 */, // S2_0_c0_c9_7 at min EL1: DBGWCR9_EL1 + REG_DBGBVR10_EL1 =32852 /* 32852 */, // S2_0_c0_c10_4 at min EL1: DBGBVR10_EL1 + REG_DBGBCR10_EL1 =32853 /* 32853 */, // S2_0_c0_c10_5 at min EL1: DBGBCR10_EL1 + REG_DBGWVR10_EL1 =32854 /* 32854 */, // S2_0_c0_c10_6 at min EL1: DBGWVR10_EL1 + REG_DBGWCR10_EL1 =32855 /* 32855 */, // S2_0_c0_c10_7 at min EL1: DBGWCR10_EL1 + REG_DBGBVR11_EL1 =32860 /* 32860 */, // S2_0_c0_c11_4 at min EL1: DBGBVR11_EL1 + REG_DBGBCR11_EL1 =32861 /* 32861 */, // S2_0_c0_c11_5 at min EL1: DBGBCR11_EL1 + REG_DBGWVR11_EL1 =32862 /* 32862 */, // S2_0_c0_c11_6 at min EL1: DBGWVR11_EL1 + REG_DBGWCR11_EL1 =32863 /* 32863 */, // S2_0_c0_c11_7 at min EL1: DBGWCR11_EL1 + REG_DBGBVR12_EL1 =32868 /* 32868 */, // S2_0_c0_c12_4 at min EL1: DBGBVR12_EL1 + REG_DBGBCR12_EL1 =32869 /* 32869 */, // S2_0_c0_c12_5 at min EL1: DBGBCR12_EL1 + REG_DBGWVR12_EL1 =32870 /* 32870 */, // S2_0_c0_c12_6 at min EL1: DBGWVR12_EL1 + REG_DBGWCR12_EL1 =32871 /* 32871 */, // S2_0_c0_c12_7 at min EL1: DBGWCR12_EL1 + REG_DBGBVR13_EL1 =32876 /* 32876 */, // S2_0_c0_c13_4 at min EL1: DBGBVR13_EL1 + REG_DBGBCR13_EL1 =32877 /* 32877 */, // S2_0_c0_c13_5 at min EL1: DBGBCR13_EL1 + REG_DBGWVR13_EL1 =32878 /* 32878 */, // S2_0_c0_c13_6 at min EL1: DBGWVR13_EL1 + REG_DBGWCR13_EL1 =32879 /* 32879 */, // S2_0_c0_c13_7 at min EL1: DBGWCR13_EL1 + REG_DBGBVR14_EL1 =32884 /* 32884 */, // S2_0_c0_c14_4 at min EL1: DBGBVR14_EL1 + REG_DBGBCR14_EL1 =32885 /* 32885 */, // S2_0_c0_c14_5 at min EL1: DBGBCR14_EL1 + REG_DBGWVR14_EL1 =32886 /* 32886 */, // S2_0_c0_c14_6 at min EL1: DBGWVR14_EL1 + REG_DBGWCR14_EL1 =32887 /* 32887 */, // S2_0_c0_c14_7 at min EL1: DBGWCR14_EL1 + REG_DBGBVR15_EL1 =32892 /* 32892 */, // S2_0_c0_c15_4 at min EL1: DBGBVR15_EL1 + REG_DBGBCR15_EL1 =32893 /* 32893 */, // S2_0_c0_c15_5 at min EL1: DBGBCR15_EL1 + REG_DBGWVR15_EL1 =32894 /* 32894 */, // S2_0_c0_c15_6 at min EL1: DBGWVR15_EL1 + REG_DBGWCR15_EL1 =32895 /* 32895 */, // S2_0_c0_c15_7 at min EL1: DBGWCR15_EL1 + REG_MDRAR_EL1 =32896 /* 32896 */, // S2_0_c1_c0_0 at min EL1: MDRAR_EL1 + REG_OSLAR_EL1 =32900 /* 32900 */, // S2_0_c1_c0_4 at min EL1: OSLAR_EL1 + REG_OSLSR_EL1 =32908 /* 32908 */, // S2_0_c1_c1_4 at min EL1: OSLSR_EL1 + REG_OSDLR_EL1 =32924 /* 32924 */, // S2_0_c1_c3_4 at min EL1: OSDLR_EL1 + REG_DBGPRCR_EL1 =32932 /* 32932 */, // S2_0_c1_c4_4 at min EL1: DBGPRCR_EL1 + REG_CLAIMSET_EL1 =33734 /* 33734 */, // S2_0_c7_c8_6 at min EL1: CLAIMSET_EL1 + REG_DBGCLAIMSET_EL1 =33734 /* 33734 */, + REG_CLAIMCLR_EL1 =33742 /* 33742 */, // S2_0_c7_c9_6 at min EL1: CLAIMCLR_EL1 + REG_DBGCLAIMCLR_EL1 =33742 /* 33742 */, + REG_AUTHSTAT_EL1 =33782 /* 33782 */, // S2_0_c7_c14_6 at min EL1: AUTHSTAT_EL1 + REG_TRCTRACEIDR =34817 /* 34817 */, + REG_TRCVICTLR =34818 /* 34818 */, + REG_TRCSEQEVR0 =34820 /* 34820 */, + REG_TRCCNTRLDVR0 =34821 /* 34821 */, + REG_TRCIMSPEC0 =34823 /* 34823 */, + REG_TRCPRGCTLR =34824 /* 34824 */, + REG_TRCQCTLR =34825 /* 34825 */, + REG_TRCVIIECTLR =34826 /* 34826 */, + REG_TRCSEQEVR1 =34828 /* 34828 */, + REG_TRCCNTRLDVR1 =34829 /* 34829 */, + REG_TRCIMSPEC1 =34831 /* 34831 */, + REG_TRCPROCSELR =34832 /* 34832 */, + REG_TRCVISSCTLR =34834 /* 34834 */, + REG_TRCSEQEVR2 =34836 /* 34836 */, + REG_TRCCNTRLDVR2 =34837 /* 34837 */, + REG_TRCIMSPEC2 =34839 /* 34839 */, + REG_TRCVIPCSSCTLR =34842 /* 34842 */, + REG_TRCCNTRLDVR3 =34845 /* 34845 */, + REG_TRCIMSPEC3 =34847 /* 34847 */, + REG_TRCCONFIGR =34848 /* 34848 */, + REG_TRCCNTCTLR0 =34853 /* 34853 */, + REG_TRCIMSPEC4 =34855 /* 34855 */, + REG_TRCCNTCTLR1 =34861 /* 34861 */, + REG_TRCIMSPEC5 =34863 /* 34863 */, + REG_TRCAUXCTLR =34864 /* 34864 */, + REG_TRCSEQRSTEVR =34868 /* 34868 */, + REG_TRCCNTCTLR2 =34869 /* 34869 */, + REG_TRCIMSPEC6 =34871 /* 34871 */, + REG_TRCSEQSTR =34876 /* 34876 */, + REG_TRCCNTCTLR3 =34877 /* 34877 */, + REG_TRCIMSPEC7 =34879 /* 34879 */, + REG_TRCEVENTCTL0R =34880 /* 34880 */, + REG_TRCVDCTLR =34882 /* 34882 */, + REG_TRCEXTINSELR =34884 /* 34884 */, + REG_TRCCNTVR0 =34885 /* 34885 */, + REG_TRCEVENTCTL1R =34888 /* 34888 */, + REG_TRCVDSACCTLR =34890 /* 34890 */, + REG_TRCEXTINSELR1 =34892 /* 34892 */, + REG_TRCCNTVR1 =34893 /* 34893 */, + REG_TRCRSR =34896 /* 34896 */, + REG_TRCVDARCCTLR =34898 /* 34898 */, + REG_TRCEXTINSELR2 =34900 /* 34900 */, + REG_TRCCNTVR2 =34901 /* 34901 */, + REG_TRCSTALLCTLR =34904 /* 34904 */, + REG_TRCEXTINSELR3 =34908 /* 34908 */, + REG_TRCCNTVR3 =34909 /* 34909 */, + REG_TRCTSCTLR =34912 /* 34912 */, + REG_TRCSYNCPR =34920 /* 34920 */, + REG_TRCCCCTLR =34928 /* 34928 */, + REG_TRCBBCTLR =34936 /* 34936 */, + REG_TRCRSCTLR16 =34945 /* 34945 */, + REG_TRCSSCCR0 =34946 /* 34946 */, + REG_TRCSSPCICR0 =34947 /* 34947 */, + REG_TRCOSLAR =34948 /* 34948 */, + REG_TRCRSCTLR17 =34953 /* 34953 */, + REG_TRCSSCCR1 =34954 /* 34954 */, + REG_TRCSSPCICR1 =34955 /* 34955 */, + REG_TRCRSCTLR2 =34960 /* 34960 */, + REG_TRCRSCTLR18 =34961 /* 34961 */, + REG_TRCSSCCR2 =34962 /* 34962 */, + REG_TRCSSPCICR2 =34963 /* 34963 */, + REG_TRCRSCTLR3 =34968 /* 34968 */, + REG_TRCRSCTLR19 =34969 /* 34969 */, + REG_TRCSSCCR3 =34970 /* 34970 */, + REG_TRCSSPCICR3 =34971 /* 34971 */, + REG_TRCRSCTLR4 =34976 /* 34976 */, + REG_TRCRSCTLR20 =34977 /* 34977 */, + REG_TRCSSCCR4 =34978 /* 34978 */, + REG_TRCSSPCICR4 =34979 /* 34979 */, + REG_TRCPDCR =34980 /* 34980 */, + REG_TRCRSCTLR5 =34984 /* 34984 */, + REG_TRCRSCTLR21 =34985 /* 34985 */, + REG_TRCSSCCR5 =34986 /* 34986 */, + REG_TRCSSPCICR5 =34987 /* 34987 */, + REG_TRCRSCTLR6 =34992 /* 34992 */, + REG_TRCRSCTLR22 =34993 /* 34993 */, + REG_TRCSSCCR6 =34994 /* 34994 */, + REG_TRCSSPCICR6 =34995 /* 34995 */, + REG_TRCRSCTLR7 =35000 /* 35000 */, + REG_TRCRSCTLR23 =35001 /* 35001 */, + REG_TRCSSCCR7 =35002 /* 35002 */, + REG_TRCSSPCICR7 =35003 /* 35003 */, + REG_TRCRSCTLR8 =35008 /* 35008 */, + REG_TRCRSCTLR24 =35009 /* 35009 */, + REG_TRCSSCSR0 =35010 /* 35010 */, + REG_TRCRSCTLR9 =35016 /* 35016 */, + REG_TRCRSCTLR25 =35017 /* 35017 */, + REG_TRCSSCSR1 =35018 /* 35018 */, + REG_TRCRSCTLR10 =35024 /* 35024 */, + REG_TRCRSCTLR26 =35025 /* 35025 */, + REG_TRCSSCSR2 =35026 /* 35026 */, + REG_TRCRSCTLR11 =35032 /* 35032 */, + REG_TRCRSCTLR27 =35033 /* 35033 */, + REG_TRCSSCSR3 =35034 /* 35034 */, + REG_TRCRSCTLR12 =35040 /* 35040 */, + REG_TRCRSCTLR28 =35041 /* 35041 */, + REG_TRCSSCSR4 =35042 /* 35042 */, + REG_TRCRSCTLR13 =35048 /* 35048 */, + REG_TRCRSCTLR29 =35049 /* 35049 */, + REG_TRCSSCSR5 =35050 /* 35050 */, + REG_TRCRSCTLR14 =35056 /* 35056 */, + REG_TRCRSCTLR30 =35057 /* 35057 */, + REG_TRCSSCSR6 =35058 /* 35058 */, + REG_TRCRSCTLR15 =35064 /* 35064 */, + REG_TRCRSCTLR31 =35065 /* 35065 */, + REG_TRCSSCSR7 =35066 /* 35066 */, + REG_TRCACVR0 =35072 /* 35072 */, + REG_TRCACVR8 =35073 /* 35073 */, + REG_TRCACATR0 =35074 /* 35074 */, + REG_TRCACATR8 =35075 /* 35075 */, + REG_TRCDVCVR0 =35076 /* 35076 */, + REG_TRCDVCVR4 =35077 /* 35077 */, + REG_TRCDVCMR0 =35078 /* 35078 */, + REG_TRCDVCMR4 =35079 /* 35079 */, + REG_TRCACVR1 =35088 /* 35088 */, + REG_TRCACVR9 =35089 /* 35089 */, + REG_TRCACATR1 =35090 /* 35090 */, + REG_TRCACATR9 =35091 /* 35091 */, + REG_TRCACVR2 =35104 /* 35104 */, + REG_TRCACVR10 =35105 /* 35105 */, + REG_TRCACATR2 =35106 /* 35106 */, + REG_TRCACATR10 =35107 /* 35107 */, + REG_TRCDVCVR1 =35108 /* 35108 */, + REG_TRCDVCVR5 =35109 /* 35109 */, + REG_TRCDVCMR1 =35110 /* 35110 */, + REG_TRCDVCMR5 =35111 /* 35111 */, + REG_TRCACVR3 =35120 /* 35120 */, + REG_TRCACVR11 =35121 /* 35121 */, + REG_TRCACATR3 =35122 /* 35122 */, + REG_TRCACATR11 =35123 /* 35123 */, + REG_TRCACVR4 =35136 /* 35136 */, + REG_TRCACVR12 =35137 /* 35137 */, + REG_TRCACATR4 =35138 /* 35138 */, + REG_TRCACATR12 =35139 /* 35139 */, + REG_TRCDVCVR2 =35140 /* 35140 */, + REG_TRCDVCVR6 =35141 /* 35141 */, + REG_TRCDVCMR2 =35142 /* 35142 */, + REG_TRCDVCMR6 =35143 /* 35143 */, + REG_TRCACVR5 =35152 /* 35152 */, + REG_TRCACVR13 =35153 /* 35153 */, + REG_TRCACATR5 =35154 /* 35154 */, + REG_TRCACATR13 =35155 /* 35155 */, + REG_TRCACVR6 =35168 /* 35168 */, + REG_TRCACVR14 =35169 /* 35169 */, + REG_TRCACATR6 =35170 /* 35170 */, + REG_TRCACATR14 =35171 /* 35171 */, + REG_TRCDVCVR3 =35172 /* 35172 */, + REG_TRCDVCVR7 =35173 /* 35173 */, + REG_TRCDVCMR3 =35174 /* 35174 */, + REG_TRCDVCMR7 =35175 /* 35175 */, + REG_TRCACVR7 =35184 /* 35184 */, + REG_TRCACVR15 =35185 /* 35185 */, + REG_TRCACATR7 =35186 /* 35186 */, + REG_TRCACATR15 =35187 /* 35187 */, + REG_TRCCIDCVR0 =35200 /* 35200 */, + REG_TRCVMIDCVR0 =35201 /* 35201 */, + REG_TRCCIDCCTLR0 =35202 /* 35202 */, + REG_TRCCIDCCTLR1 =35210 /* 35210 */, + REG_TRCCIDCVR1 =35216 /* 35216 */, + REG_TRCVMIDCVR1 =35217 /* 35217 */, + REG_TRCVMIDCCTLR0 =35218 /* 35218 */, + REG_TRCVMIDCCTLR1 =35226 /* 35226 */, + REG_TRCCIDCVR2 =35232 /* 35232 */, + REG_TRCVMIDCVR2 =35233 /* 35233 */, + REG_TRCCIDCVR3 =35248 /* 35248 */, + REG_TRCVMIDCVR3 =35249 /* 35249 */, + REG_TRCCIDCVR4 =35264 /* 35264 */, + REG_TRCVMIDCVR4 =35265 /* 35265 */, + REG_TRCCIDCVR5 =35280 /* 35280 */, + REG_TRCVMIDCVR5 =35281 /* 35281 */, + REG_TRCCIDCVR6 =35296 /* 35296 */, + REG_TRCVMIDCVR6 =35297 /* 35297 */, + REG_TRCCIDCVR7 =35312 /* 35312 */, + REG_TRCVMIDCVR7 =35313 /* 35313 */, + REG_TRCITCTRL =35716 /* 35716 */, + REG_TRCCLAIMSET =35782 /* 35782 */, + REG_TRCCLAIMCLR =35790 /* 35790 */, + REG_TRCLAR =35814 /* 35814 */, + REG_TEECR32_EL1 =36864 /* 36864 */, // S2_2_c0_c0_0 at min EL1: TEECR32_EL1 + REG_TEEHBR32_EL1 =36992 /* 36992 */, // S2_2_c1_c0_0 at min EL1: TEEHBR32_EL1 + REG_MDCCSR_EL0 =38920 /* 38920 */, // S2_3_c0_c1_0 at min EL1: MDCCSR_EL0 + REG_MDDTR_EL0 =38944 /* 38944 */, // S2_3_c0_c4_0 at min EL1: MDDTR_EL0 + REG_DBGDTR_EL0 =38944 /* 38944 */, + REG_MDDTRTX_EL0 =38952 /* 38952 */, // S2_3_c0_c5_0 at min EL1: MDDTRTX_EL0 + REG_DBGDTRTX_EL0 =38952 /* 38952 */, + REG_DBGVCR32_EL2 =41016 /* 41016 */, // S2_4_c0_c7_0 at min EL2: DBGVCR32_EL2 + REG_MIDR_EL1 =49152 /* 49152 */, // S3_0_c0_c0_0 at min EL1: MIDR_EL1 + REG_MPIDR_EL1 =49157 /* 49157 */, // S3_0_c0_c0_5 at min EL1: MPIDR_EL1 + REG_REVIDR_EL1 =49158 /* 49158 */, // S3_0_c0_c0_6 at min EL1: REVIDR_EL1 + REG_ID_PFR0_EL1 =49160 /* 49160 */, // S3_0_c0_c1_0 at min EL1: ID_PFR0_EL1 + REG_ID_PFR1_EL1 =49161 /* 49161 */, // S3_0_c0_c1_1 at min EL1: ID_PFR1_EL1 + REG_ID_DFR0_EL1 =49162 /* 49162 */, // S3_0_c0_c1_2 at min EL1: ID_DFR0_EL1 + REG_ID_AFR0_EL1 =49163 /* 49163 */, // S3_0_c0_c1_3 at min EL1: ID_AFR0_EL1 + REG_ID_MMFR0_EL1 =49164 /* 49164 */, // S3_0_c0_c1_4 at min EL1: ID_MMFR0_EL1 + REG_ID_MMFR1_EL1 =49165 /* 49165 */, // S3_0_c0_c1_5 at min EL1: ID_MMFR1_EL1 + REG_ID_MMFR2_EL1 =49166 /* 49166 */, // S3_0_c0_c1_6 at min EL1: ID_MMFR2_EL1 + REG_ID_MMFR3_EL1 =49167 /* 49167 */, // S3_0_c0_c1_7 at min EL1: ID_MMFR3_EL1 + REG_ID_ISAR0_EL1 =49168 /* 49168 */, // S3_0_c0_c2_0 at min EL1: ID_ISAR0_EL1 + REG_ID_ISAR1_EL1 =49169 /* 49169 */, // S3_0_c0_c2_1 at min EL1: ID_ISAR1_EL1 + REG_ID_ISAR2_EL1 =49170 /* 49170 */, // S3_0_c0_c2_2 at min EL1: ID_ISAR2_EL1 + REG_ID_ISAR3_EL1 =49171 /* 49171 */, // S3_0_c0_c2_3 at min EL1: ID_ISAR3_EL1 + REG_ID_ISAR4_EL1 =49172 /* 49172 */, // S3_0_c0_c2_4 at min EL1: ID_ISAR4_EL1 + REG_ID_ISAR5_EL1 =49173 /* 49173 */, // S3_0_c0_c2_5 at min EL1: ID_ISAR5_EL1 + REG_ID_MMFR4_EL1 =49174 /* 49174 */, // S3_0_c0_c2_6 at min EL1: ID_MMFR4_EL1 + REG_ID_ISAR6_EL1 =49175 /* 49175 */, // S3_0_c0_c2_7 at min EL1: ID_ISAR6_EL1 + REG_MVFR0_EL1 =49176 /* 49176 */, // S3_0_c0_c3_0 at min EL1: MVFR0_EL1 + REG_MVFR1_EL1 =49177 /* 49177 */, // S3_0_c0_c3_1 at min EL1: MVFR1_EL1 + REG_MVFR2_EL1 =49178 /* 49178 */, // S3_0_c0_c3_2 at min EL1: MVFR2_EL1 + REG_ID_AA32RES3_EL1 =49179 /* 49179 */, // S3_0_c0_c3_3 at min EL1: ID_AA32RES3_EL1 + REG_ID_PFR2_EL1 =49180 /* 49180 */, // S3_0_c0_c3_4 at min EL1: ID_PFR2_EL1 + REG_ID_AA32RES5_EL1 =49181 /* 49181 */, // S3_0_c0_c3_5 at min EL1: ID_AA32RES5_EL1 + REG_ID_AA32RES6_EL1 =49182 /* 49182 */, // S3_0_c0_c3_6 at min EL1: ID_AA32RES6_EL1 + REG_ID_AA32RES7_EL1 =49183 /* 49183 */, // S3_0_c0_c3_7 at min EL1: ID_AA32RES7_EL1 + REG_ID_AA64PFR0_EL1 =49184 /* 49184 */, // S3_0_c0_c4_0 at min EL1: ID_AA64PFR0_EL1 + REG_ID_AA64PFR1_EL1 =49185 /* 49185 */, // S3_0_c0_c4_1 at min EL1: ID_AA64PFR1_EL1 + REG_ID_AA64PFR2_EL1 =49186 /* 49186 */, // S3_0_c0_c4_2 at min EL1: ID_AA64PFR2_EL1 + REG_ID_AA64PFR3_EL1 =49187 /* 49187 */, // S3_0_c0_c4_3 at min EL1: ID_AA64PFR3_EL1 + REG_ID_AA64ZFR0_EL1 =49188 /* 49188 */, // S3_0_c0_c4_4 at min EL1: ID_AA64ZFR0_EL1 + REG_ID_AA64SMFR0_EL1 =49189 /* 49189 */, // S3_0_c0_c4_5 at min EL1: ID_AA64SMFR0_EL1 + REG_ID_AA64ZFR2_EL1 =49190 /* 49190 */, // S3_0_c0_c4_6 at min EL1: ID_AA64ZFR2_EL1 + REG_ID_AA64ZFR3_EL1 =49191 /* 49191 */, // S3_0_c0_c4_7 at min EL1: ID_AA64ZFR3_EL1 + REG_ID_AA64DFR0_EL1 =49192 /* 49192 */, // S3_0_c0_c5_0 at min EL1: ID_AA64DFR0_EL1 + REG_ID_AA64DFR1_EL1 =49193 /* 49193 */, // S3_0_c0_c5_1 at min EL1: ID_AA64DFR1_EL1 + REG_ID_AA64DFR2_EL1 =49194 /* 49194 */, // S3_0_c0_c5_2 at min EL1: ID_AA64DFR2_EL1 + REG_ID_AA64DFR3_EL1 =49195 /* 49195 */, // S3_0_c0_c5_3 at min EL1: ID_AA64DFR3_EL1 + REG_ID_AA64AFR0_EL1 =49196 /* 49196 */, // S3_0_c0_c5_4 at min EL1: ID_AA64AFR0_EL1 + REG_ID_AA64AFR1_EL1 =49197 /* 49197 */, // S3_0_c0_c5_5 at min EL1: ID_AA64AFR1_EL1 + REG_ID_AA64AFR2_EL1 =49198 /* 49198 */, // S3_0_c0_c5_6 at min EL1: ID_AA64AFR2_EL1 + REG_ID_AA64AFR3_EL1 =49199 /* 49199 */, // S3_0_c0_c5_7 at min EL1: ID_AA64AFR3_EL1 + REG_ID_AA64ISAR0_EL1 =49200 /* 49200 */, // S3_0_c0_c6_0 at min EL1: ID_AA64ISAR0_EL1 + REG_ID_AA64ISAR1_EL1 =49201 /* 49201 */, // S3_0_c0_c6_1 at min EL1: ID_AA64ISAR1_EL1 + REG_ID_AA64ISAR2_EL1 =49202 /* 49202 */, // S3_0_c0_c6_2 at min EL1: ID_AA64ISAR2_EL1 + REG_ID_AA64ISAR3_EL1 =49203 /* 49203 */, // S3_0_c0_c6_3 at min EL1: ID_AA64ISAR3_EL1 + REG_ID_AA64ISAR4_EL1 =49204 /* 49204 */, // S3_0_c0_c6_4 at min EL1: ID_AA64ISAR4_EL1 + REG_ID_AA64ISAR5_EL1 =49205 /* 49205 */, // S3_0_c0_c6_5 at min EL1: ID_AA64ISAR5_EL1 + REG_ID_AA64ISAR6_EL1 =49206 /* 49206 */, // S3_0_c0_c6_6 at min EL1: ID_AA64ISAR6_EL1 + REG_ID_AA64ISAR7_EL1 =49207 /* 49207 */, // S3_0_c0_c6_7 at min EL1: ID_AA64ISAR7_EL1 + REG_ID_AA64MMFR0_EL1 =49208 /* 49208 */, // S3_0_c0_c7_0 at min EL1: ID_AA64MMFR0_EL1 + REG_ID_AA64MMFR1_EL1 =49209 /* 49209 */, // S3_0_c0_c7_1 at min EL1: ID_AA64MMFR1_EL1 + REG_ID_AA64MMFR2_EL1 =49210 /* 49210 */, // S3_0_c0_c7_2 at min EL1: ID_AA64MMFR2_EL1 + REG_ID_AA64MMFR3_EL1 =49211 /* 49211 */, // S3_0_c0_c7_3 at min EL1: ID_AA64MMFR3_EL1 + REG_ID_AA64MMFR4_EL1 =49212 /* 49212 */, // S3_0_c0_c7_4 at min EL1: ID_AA64MMFR4_EL1 + REG_ID_AA64MMFR5_EL1 =49213 /* 49213 */, // S3_0_c0_c7_5 at min EL1: ID_AA64MMFR5_EL1 + REG_ID_AA64MMFR6_EL1 =49214 /* 49214 */, // S3_0_c0_c7_6 at min EL1: ID_AA64MMFR6_EL1 + REG_ID_AA64MMFR7_EL1 =49215 /* 49215 */, // S3_0_c0_c7_7 at min EL1: ID_AA64MMFR7_EL1 + REG_SCTLR_EL21 =49280 /* 49280 */, // S3_0_c1_c0_0 at min EL1: SCTLR_EL21 + REG_SCTLR_EL1 =49280 /* 49280 */, + REG_ACTLR_EL21 =49281 /* 49281 */, // S3_0_c1_c0_1 at min EL1: ACTLR_EL21 + REG_ACTLR_EL1 =49281 /* 49281 */, + REG_CPTR_EL21 =49282 /* 49282 */, // S3_0_c1_c0_2 at min EL1: CPTR_EL21 + REG_CPACR_EL1 =49282 /* 49282 */, + REG_RGSR_EL1 =49285 /* 49285 */, + REG_GCR_EL1 =49286 /* 49286 */, + REG_TRFCR_EL1 =49297 /* 49297 */, + REG_SMPRI_EL1 =49300 /* 49300 */, // S3_0_c1_c2_4 at min EL1: SMPRI_EL1 + REG_SMCR_EL21 =49302 /* 49302 */, // S3_0_c1_c2_6 at min EL1: SMCR_EL21 + REG_TTBR0_EL21 =49408 /* 49408 */, // S3_0_c2_c0_0 at min EL1: TTBR0_EL21 + REG_TTBR0_EL1 =49408 /* 49408 */, + REG_TTBR1_EL21 =49409 /* 49409 */, // S3_0_c2_c0_1 at min EL1: TTBR1_EL21 + REG_TTBR1_EL1 =49409 /* 49409 */, + REG_TCR_EL21 =49410 /* 49410 */, // S3_0_c2_c0_2 at min EL1: TCR_EL21 + REG_TCR_EL1 =49410 /* 49410 */, + REG_APIAKEYLO_EL21 =49416 /* 49416 */, // S3_0_c2_c1_0 at min EL1: APIAKeyLo_EL21 + REG_APIAKEYLO_EL1 =49416 /* 49416 */, + REG_APIAKEYHI_EL21 =49417 /* 49417 */, // S3_0_c2_c1_1 at min EL1: APIAKeyHi_EL21 + REG_APIAKEYHI_EL1 =49417 /* 49417 */, + REG_APIBKEYLO_EL21 =49418 /* 49418 */, // S3_0_c2_c1_2 at min EL1: APIBKeyLo_EL21 + REG_APIBKEYLO_EL1 =49418 /* 49418 */, + REG_APIBKEYHI_EL21 =49419 /* 49419 */, // S3_0_c2_c1_3 at min EL1: APIBKeyHi_EL21 + REG_APIBKEYHI_EL1 =49419 /* 49419 */, + REG_APDAKEYLO_EL21 =49424 /* 49424 */, // S3_0_c2_c2_0 at min EL1: APDAKeyLo_EL21 + REG_APDAKEYLO_EL1 =49424 /* 49424 */, + REG_APDAKEYHI_EL21 =49425 /* 49425 */, // S3_0_c2_c2_1 at min EL1: APDAKeyHi_EL21 + REG_APDAKEYHI_EL1 =49425 /* 49425 */, + REG_APDBKEYLO_EL21 =49426 /* 49426 */, // S3_0_c2_c2_2 at min EL1: APDBKeyLo_EL21 + REG_APDBKEYLO_EL1 =49426 /* 49426 */, + REG_APDBKEYHI_EL21 =49427 /* 49427 */, // S3_0_c2_c2_3 at min EL1: APDBKeyHi_EL21 + REG_APDBKEYHI_EL1 =49427 /* 49427 */, + REG_APGAKEYLO_EL21 =49432 /* 49432 */, // S3_0_c2_c3_0 at min EL1: APGAKeyLo_EL21 + REG_APGAKEYLO_EL1 =49432 /* 49432 */, + REG_APGAKEYHI_EL21 =49433 /* 49433 */, // S3_0_c2_c3_1 at min EL1: APGAKeyHi_EL21 + REG_APGAKEYHI_EL1 =49433 /* 49433 */, + REG_SPSR_EL21 =49664 /* 49664 */, // S3_0_c4_c0_0 at min EL1: SPSR_EL21 + REG_SPSR_EL1 =49664 /* 49664 */, + REG_ELR_EL21 =49665 /* 49665 */, // S3_0_c4_c0_1 at min EL1: ELR_EL21 + REG_ELR_EL1 =49665 /* 49665 */, + REG_SP_EL0 =49672 /* 49672 */, // S3_0_c4_c1_0 at min EL1: SP_EL0 + REG_SPSEL =49680 /* 49680 */, // S3_0_c4_c2_0 at min EL1: SPSEL + REG_NESTEDCURRENTEL =49682 /* 49682 */, // S3_0_c4_c2_2 at min EL1: NestedCurrentEL + REG_CURRENTEL =49682 /* 49682 */, + REG_PAN =49683 /* 49683 */, // S3_0_c4_c2_3 at min EL1: PAN + REG_UAO =49684 /* 49684 */, // S3_0_c4_c2_4 at min EL1: UAO + REG_ICV_PMR_EL1 =49712 /* 49712 */, // S3_0_c4_c6_0 at min EL1: ICV_PMR_EL1 + REG_ICC_PMR_EL1 =49712 /* 49712 */, + REG_AFSR0_EL21 =49800 /* 49800 */, // S3_0_c5_c1_0 at min EL1: AFSR0_EL21 + REG_AFSR0_EL1 =49800 /* 49800 */, + REG_AFSR1_EL21 =49801 /* 49801 */, // S3_0_c5_c1_1 at min EL1: AFSR1_EL21 + REG_AFSR1_EL1 =49801 /* 49801 */, + REG_ESR_EL21 =49808 /* 49808 */, // S3_0_c5_c2_0 at min EL1: ESR_EL21 + REG_ESR_EL1 =49808 /* 49808 */, + REG_ERRIDR_EL1 =49816 /* 49816 */, // S3_0_c5_c3_0 at min EL1: ERRIDR_EL1 + REG_ERRSELR_EL1 =49817 /* 49817 */, + REG_ERXCTLR_EL1 =49825 /* 49825 */, + REG_ERXSTATUS_EL1 =49826 /* 49826 */, + REG_ERXADDR_EL1 =49827 /* 49827 */, + REG_ERXPFGCTL_EL1 =49829 /* 49829 */, + REG_ERXPFGCDN_EL1 =49830 /* 49830 */, + REG_ERXMISC0_EL1 =49832 /* 49832 */, + REG_ERXMISC1_EL1 =49833 /* 49833 */, + REG_ERXMISC2_EL1 =49834 /* 49834 */, + REG_ERXMISC3_EL1 =49835 /* 49835 */, + REG_ERXTS_EL1 =49839 /* 49839 */, + REG_TFSR_EL1 =49840 /* 49840 */, + REG_TFSRE0_EL1 =49841 /* 49841 */, + REG_FAR_EL21 =49920 /* 49920 */, // S3_0_c6_c0_0 at min EL1: FAR_EL21 + REG_FAR_EL1 =49920 /* 49920 */, + REG_PAR_EL1 =50080 /* 50080 */, // S3_0_c7_c4_0 at min EL1: PAR_EL1 + REG_PMSCR_EL1 =50376 /* 50376 */, + REG_PMSICR_EL1 =50378 /* 50378 */, + REG_PMSIRR_EL1 =50379 /* 50379 */, + REG_PMSFCR_EL1 =50380 /* 50380 */, + REG_PMSEVFR_EL1 =50381 /* 50381 */, + REG_PMSLATFR_EL1 =50382 /* 50382 */, + REG_PMSIDR_EL1 =50383 /* 50383 */, + REG_PMBLIMITR_EL1 =50384 /* 50384 */, + REG_PMBPTR_EL1 =50385 /* 50385 */, + REG_PMBSR_EL1 =50387 /* 50387 */, + REG_PMBIDR_EL1 =50391 /* 50391 */, + REG_TRBLIMITR_EL1 =50392 /* 50392 */, + REG_TRBPTR_EL1 =50393 /* 50393 */, + REG_TRBBASER_EL1 =50394 /* 50394 */, + REG_TRBSR_EL1 =50395 /* 50395 */, + REG_TRBMAR_EL1 =50396 /* 50396 */, + REG_TRBTRG_EL1 =50398 /* 50398 */, + REG_PMINTENSET_EL1 =50417 /* 50417 */, + REG_PMINTENCLR_EL1 =50418 /* 50418 */, + REG_PMMIR_EL1 =50422 /* 50422 */, + REG_MAIR_EL21 =50448 /* 50448 */, // S3_0_c10_c2_0 at min EL1: MAIR_EL21 + REG_MAIR_EL1 =50448 /* 50448 */, + REG_AMAIR_EL21 =50456 /* 50456 */, // S3_0_c10_c3_0 at min EL1: AMAIR_EL21 + REG_AMAIR_EL1 =50456 /* 50456 */, + REG_LORSA_EL1 =50464 /* 50464 */, // S3_0_c10_c4_0 at min EL1: LORSA_EL1 + REG_LOREA_EL1 =50465 /* 50465 */, // S3_0_c10_c4_1 at min EL1: LOREA_EL1 + REG_LORN_EL1 =50466 /* 50466 */, // S3_0_c10_c4_2 at min EL1: LORN_EL1 + REG_LORC_EL1 =50467 /* 50467 */, // S3_0_c10_c4_3 at min EL1: LORC_EL1 + REG_LORID_EL1 =50471 /* 50471 */, // S3_0_c10_c4_7 at min EL1: LORID_EL1 + REG_MPAM1_EL1 =50472 /* 50472 */, + REG_MPAM0_EL1 =50473 /* 50473 */, + REG_CTRR_C_LWR_EL21 =50560 /* 50560 */, // S3_0_c11_c0_0 at min EL1: CTRR_C_LWR_EL21 + REG_CTRR_C_UPR_EL21 =50561 /* 50561 */, // S3_0_c11_c0_1 at min EL1: CTRR_C_UPR_EL21 + REG_CTRR_D_LWR_EL21 =50562 /* 50562 */, // S3_0_c11_c0_2 at min EL1: CTRR_D_LWR_EL21 + REG_CTRR_D_UPR_EL21 =50563 /* 50563 */, // S3_0_c11_c0_3 at min EL1: CTRR_D_UPR_EL21 + REG_CTRR_C_LWR_EL12 =50564 /* 50564 */, // S3_0_c11_c0_4 at min EL2: CTRR_C_LWR_EL12 + REG_CTRR_C_UPR_EL12 =50565 /* 50565 */, // S3_0_c11_c0_5 at min EL2: CTRR_C_UPR_EL12 + REG_CTRR_D_LWR_EL12 =50566 /* 50566 */, // S3_0_c11_c0_6 at min EL2: CTRR_D_LWR_EL12 + REG_CTRR_D_UPR_EL12 =50567 /* 50567 */, // S3_0_c11_c0_7 at min EL2: CTRR_D_UPR_EL12 + REG_CTRR_C_LWR_EL2 =50568 /* 50568 */, // S3_0_c11_c1_0 at min EL2: CTRR_C_LWR_EL2 + REG_CTRR_C_UPR_EL2 =50569 /* 50569 */, // S3_0_c11_c1_1 at min EL2: CTRR_C_UPR_EL2 + REG_CTRR_D_LWR_EL2 =50570 /* 50570 */, // S3_0_c11_c1_2 at min EL2: CTRR_D_LWR_EL2 + REG_CTRR_D_UPR_EL2 =50571 /* 50571 */, // S3_0_c11_c1_3 at min EL2: CTRR_D_UPR_EL2 + REG_CTRR_C_CTL_EL21 =50572 /* 50572 */, // S3_0_c11_c1_4 at min EL1: CTRR_C_CTL_EL21 + REG_CTRR_D_CTL_EL21 =50573 /* 50573 */, // S3_0_c11_c1_5 at min EL1: CTRR_D_CTL_EL21 + REG_CTRR_C_CTL_EL12 =50574 /* 50574 */, // S3_0_c11_c1_6 at min EL2: CTRR_C_CTL_EL12 + REG_CTRR_D_CTL_EL12 =50575 /* 50575 */, // S3_0_c11_c1_7 at min EL2: CTRR_D_CTL_EL12 + REG_CTRR_C_CTL_EL2 =50576 /* 50576 */, // S3_0_c11_c2_0 at min EL2: CTRR_C_CTL_EL2 + REG_CTRR_D_CTL_EL2 =50577 /* 50577 */, // S3_0_c11_c2_1 at min EL2: CTRR_D_CTL_EL2 + REG_CTXR_A_LWR_EL21 =50578 /* 50578 */, // S3_0_c11_c2_2 at min EL1: CTXR_A_LWR_EL21 + REG_CTXR_A_UPR_EL21 =50579 /* 50579 */, // S3_0_c11_c2_3 at min EL1: CTXR_A_UPR_EL21 + REG_CTXR_B_LWR_EL21 =50580 /* 50580 */, // S3_0_c11_c2_4 at min EL1: CTXR_B_LWR_EL21 + REG_CTXR_B_UPR_EL21 =50581 /* 50581 */, // S3_0_c11_c2_5 at min EL1: CTXR_B_UPR_EL21 + REG_CTXR_C_LWR_EL21 =50582 /* 50582 */, // S3_0_c11_c2_6 at min EL1: CTXR_C_LWR_EL21 + REG_CTXR_C_UPR_EL21 =50583 /* 50583 */, // S3_0_c11_c2_7 at min EL1: CTXR_C_UPR_EL21 + REG_CTXR_D_LWR_EL21 =50584 /* 50584 */, // S3_0_c11_c3_0 at min EL1: CTXR_D_LWR_EL21 + REG_CTXR_D_UPR_EL21 =50585 /* 50585 */, // S3_0_c11_c3_1 at min EL1: CTXR_D_UPR_EL21 + REG_CTXR_A_LWR_EL12 =50586 /* 50586 */, // S3_0_c11_c3_2 at min EL2: CTXR_A_LWR_EL12 + REG_CTXR_A_UPR_EL12 =50587 /* 50587 */, // S3_0_c11_c3_3 at min EL2: CTXR_A_UPR_EL12 + REG_CTXR_B_LWR_EL12 =50588 /* 50588 */, // S3_0_c11_c3_4 at min EL2: CTXR_B_LWR_EL12 + REG_CTXR_B_UPR_EL12 =50589 /* 50589 */, // S3_0_c11_c3_5 at min EL2: CTXR_B_UPR_EL12 + REG_CTXR_C_LWR_EL12 =50590 /* 50590 */, // S3_0_c11_c3_6 at min EL2: CTXR_C_LWR_EL12 + REG_CTXR_C_UPR_EL12 =50591 /* 50591 */, // S3_0_c11_c3_7 at min EL2: CTXR_C_UPR_EL12 + REG_CTXR_D_LWR_EL12 =50592 /* 50592 */, // S3_0_c11_c4_0 at min EL2: CTXR_D_LWR_EL12 + REG_CTXR_D_UPR_EL12 =50593 /* 50593 */, // S3_0_c11_c4_1 at min EL2: CTXR_D_UPR_EL12 + REG_CTXR_A_LWR_EL2 =50594 /* 50594 */, // S3_0_c11_c4_2 at min EL2: CTXR_A_LWR_EL2 + REG_CTXR_A_UPR_EL2 =50595 /* 50595 */, // S3_0_c11_c4_3 at min EL2: CTXR_A_UPR_EL2 + REG_CTXR_B_LWR_EL2 =50596 /* 50596 */, // S3_0_c11_c4_4 at min EL2: CTXR_B_LWR_EL2 + REG_CTXR_B_UPR_EL2 =50597 /* 50597 */, // S3_0_c11_c4_5 at min EL2: CTXR_B_UPR_EL2 + REG_CTXR_C_LWR_EL2 =50598 /* 50598 */, // S3_0_c11_c4_6 at min EL2: CTXR_C_LWR_EL2 + REG_CTXR_C_UPR_EL2 =50599 /* 50599 */, // S3_0_c11_c4_7 at min EL2: CTXR_C_UPR_EL2 + REG_CTXR_D_LWR_EL2 =50600 /* 50600 */, // S3_0_c11_c5_0 at min EL2: CTXR_D_LWR_EL2 + REG_CTXR_D_UPR_EL2 =50601 /* 50601 */, // S3_0_c11_c5_1 at min EL2: CTXR_D_UPR_EL2 + REG_CTXR_A_CTL_EL21 =50602 /* 50602 */, // S3_0_c11_c5_2 at min EL1: CTXR_A_CTL_EL21 + REG_CTXR_B_CTL_EL21 =50603 /* 50603 */, // S3_0_c11_c5_3 at min EL1: CTXR_B_CTL_EL21 + REG_CTXR_C_CTL_EL21 =50604 /* 50604 */, // S3_0_c11_c5_4 at min EL1: CTXR_C_CTL_EL21 + REG_CTXR_D_CTL_EL21 =50605 /* 50605 */, // S3_0_c11_c5_5 at min EL1: CTXR_D_CTL_EL21 + REG_CTXR_A_CTL_EL12 =50606 /* 50606 */, // S3_0_c11_c5_6 at min EL2: CTXR_A_CTL_EL12 + REG_CTXR_B_CTL_EL12 =50607 /* 50607 */, // S3_0_c11_c5_7 at min EL2: CTXR_B_CTL_EL12 + REG_CTXR_C_CTL_EL12 =50608 /* 50608 */, // S3_0_c11_c6_0 at min EL2: CTXR_C_CTL_EL12 + REG_CTXR_D_CTL_EL12 =50609 /* 50609 */, // S3_0_c11_c6_1 at min EL2: CTXR_D_CTL_EL12 + REG_CTXR_A_CTL_EL2 =50610 /* 50610 */, // S3_0_c11_c6_2 at min EL2: CTXR_A_CTL_EL2 + REG_CTXR_B_CTL_EL2 =50611 /* 50611 */, // S3_0_c11_c6_3 at min EL2: CTXR_B_CTL_EL2 + REG_CTXR_C_CTL_EL2 =50612 /* 50612 */, // S3_0_c11_c6_4 at min EL2: CTXR_C_CTL_EL2 + REG_CTXR_D_CTL_EL2 =50613 /* 50613 */, // S3_0_c11_c6_5 at min EL2: CTXR_D_CTL_EL2 + REG_ACC_CTRR_C_LWR_EL2 =50614 /* 50614 */, // S3_0_c11_c6_6 at min EL2: ACC_CTRR_C_LWR_EL2 + REG_ACC_CTRR_C_UPR_EL2 =50615 /* 50615 */, // S3_0_c11_c6_7 at min EL2: ACC_CTRR_C_UPR_EL2 + REG_ACC_CTRR_D_LWR_EL2 =50616 /* 50616 */, // S3_0_c11_c7_0 at min EL2: ACC_CTRR_D_LWR_EL2 + REG_ACC_CTRR_D_UPR_EL2 =50617 /* 50617 */, // S3_0_c11_c7_1 at min EL2: ACC_CTRR_D_UPR_EL2 + REG_ACC_CTXR_A_LWR_EL2 =50618 /* 50618 */, // S3_0_c11_c7_2 at min EL2: ACC_CTXR_A_LWR_EL2 + REG_ACC_CTXR_A_UPR_EL2 =50619 /* 50619 */, // S3_0_c11_c7_3 at min EL2: ACC_CTXR_A_UPR_EL2 + REG_ACC_CTXR_B_LWR_EL2 =50620 /* 50620 */, // S3_0_c11_c7_4 at min EL2: ACC_CTXR_B_LWR_EL2 + REG_ACC_CTXR_B_UPR_EL2 =50621 /* 50621 */, // S3_0_c11_c7_5 at min EL2: ACC_CTXR_B_UPR_EL2 + REG_ACC_CTXR_C_LWR_EL2 =50622 /* 50622 */, // S3_0_c11_c7_6 at min EL2: ACC_CTXR_C_LWR_EL2 + REG_ACC_CTXR_C_UPR_EL2 =50623 /* 50623 */, // S3_0_c11_c7_7 at min EL2: ACC_CTXR_C_UPR_EL2 + REG_ACC_CTXR_D_LWR_EL2 =50624 /* 50624 */, // S3_0_c11_c8_0 at min EL2: ACC_CTXR_D_LWR_EL2 + REG_ACC_CTXR_D_UPR_EL2 =50625 /* 50625 */, // S3_0_c11_c8_1 at min EL2: ACC_CTXR_D_UPR_EL2 + REG_ACC_CTRR_C_CTL_EL2 =50626 /* 50626 */, // S3_0_c11_c8_2 at min EL2: ACC_CTRR_C_CTL_EL2 + REG_ACC_CTRR_D_CTL_EL2 =50627 /* 50627 */, // S3_0_c11_c8_3 at min EL2: ACC_CTRR_D_CTL_EL2 + REG_ACC_CTXR_A_CTL_EL2 =50628 /* 50628 */, // S3_0_c11_c8_4 at min EL2: ACC_CTXR_A_CTL_EL2 + REG_ACC_CTXR_B_CTL_EL2 =50629 /* 50629 */, // S3_0_c11_c8_5 at min EL2: ACC_CTXR_B_CTL_EL2 + REG_ACC_CTXR_C_CTL_EL2 =50630 /* 50630 */, // S3_0_c11_c8_6 at min EL2: ACC_CTXR_C_CTL_EL2 + REG_ACC_CTXR_D_CTL_EL2 =50631 /* 50631 */, // S3_0_c11_c8_7 at min EL2: ACC_CTXR_D_CTL_EL2 + REG_VBAR_EL21 =50688 /* 50688 */, // S3_0_c12_c0_0 at min EL1: VBAR_EL21 + REG_VBAR_EL1 =50688 /* 50688 */, + REG_RVBAR_EL1 =50689 /* 50689 */, // S3_0_c12_c0_1 at min EL1: RVBAR_EL1 + REG_RMR_EL1 =50690 /* 50690 */, // S3_0_c12_c0_2 at min EL1: RMR_EL1 + REG_ISR_EL1 =50696 /* 50696 */, // S3_0_c12_c1_0 at min EL1: ISR_EL1 + REG_DISR_EL1 =50697 /* 50697 */, // S3_0_c12_c1_1 at min EL1: DISR_EL1 + REG_ICV_IAR0_EL1 =50752 /* 50752 */, // S3_0_c12_c8_0 at min EL1: ICV_IAR0_EL1 + REG_ICV_EOIR0_EL1 =50753 /* 50753 */, // S3_0_c12_c8_1 at min EL1: ICV_EOIR0_EL1 + REG_ICC_EOIR0_EL1 =50753 /* 50753 */, + REG_ICV_HPPIR0_EL1 =50754 /* 50754 */, // S3_0_c12_c8_2 at min EL1: ICV_HPPIR0_EL1 + REG_ICV_BPR0_EL1 =50755 /* 50755 */, // S3_0_c12_c8_3 at min EL1: ICV_BPR0_EL1 + REG_ICC_BPR0_EL1 =50755 /* 50755 */, + REG_ICC_AP0R0_EL1 =50756 /* 50756 */, // S3_0_c12_c8_4 at min EL1: ICC_AP0R0_EL1 + REG_ICC_AP0R1_EL1 =50757 /* 50757 */, + REG_ICC_AP0R2_EL1 =50758 /* 50758 */, + REG_ICC_AP0R3_EL1 =50759 /* 50759 */, + REG_ICC_AP1R0_EL1 =50760 /* 50760 */, // S3_0_c12_c9_0 at min EL1: ICC_AP1R0_EL1 + REG_ICC_AP1R1_EL1 =50761 /* 50761 */, + REG_ICC_AP1R2_EL1 =50762 /* 50762 */, + REG_ICC_AP1R3_EL1 =50763 /* 50763 */, + REG_ICV_DIR_EL1 =50777 /* 50777 */, // S3_0_c12_c11_1 at min EL1: ICV_DIR_EL1 + REG_ICC_DIR_EL1 =50777 /* 50777 */, + REG_ICV_RPR_EL1 =50779 /* 50779 */, // S3_0_c12_c11_3 at min EL1: ICV_RPR_EL1 + REG_ICC_SGI1R_EL1 =50781 /* 50781 */, // S3_0_c12_c11_5 at min EL1: ICC_SGI1R_EL1 + REG_ICC_ASGI1R_EL1 =50782 /* 50782 */, // S3_0_c12_c11_6 at min EL1: ICC_ASGI1R_EL1 + REG_ICC_SGI0R_EL1 =50783 /* 50783 */, // S3_0_c12_c11_7 at min EL1: ICC_SGI0R_EL1 + REG_ICV_IAR1_EL1 =50784 /* 50784 */, // S3_0_c12_c12_0 at min EL1: ICV_IAR1_EL1 + REG_ICV_EOIR1_EL1 =50785 /* 50785 */, // S3_0_c12_c12_1 at min EL1: ICV_EOIR1_EL1 + REG_ICC_EOIR1_EL1 =50785 /* 50785 */, + REG_ICV_HPPIR1_EL1 =50786 /* 50786 */, // S3_0_c12_c12_2 at min EL1: ICV_HPPIR1_EL1 + REG_ICV_BPR1_EL1 =50787 /* 50787 */, // S3_0_c12_c12_3 at min EL1: ICV_BPR1_EL1 + REG_ICC_BPR1_EL1 =50787 /* 50787 */, + REG_ICV_CTLR_EL1 =50788 /* 50788 */, // S3_0_c12_c12_4 at min EL1: ICV_CTLR_EL1 + REG_ICC_CTLR_EL1 =50788 /* 50788 */, + REG_ICC_SRE_EL1 =50789 /* 50789 */, // S3_0_c12_c12_5 at min EL1: ICC_SRE_EL1 + REG_ICV_IGRPEN0_EL1 =50790 /* 50790 */, // S3_0_c12_c12_6 at min EL1: ICV_IGRPEN0_EL1 + REG_ICC_IGRPEN0_EL1 =50790 /* 50790 */, + REG_ICV_IGRPEN1_EL1 =50791 /* 50791 */, // S3_0_c12_c12_7 at min EL1: ICV_IGRPEN1_EL1 + REG_ICC_IGRPEN1_EL1 =50791 /* 50791 */, + REG_ICC_SEIEN_EL1 =50792 /* 50792 */, + REG_CONTEXTIDR_EL21 =50817 /* 50817 */, // S3_0_c13_c0_1 at min EL1: CONTEXTIDR_EL21 + REG_CONTEXTIDR_EL1 =50817 /* 50817 */, + REG_TPIDR_EL1 =50820 /* 50820 */, // S3_0_c13_c0_4 at min EL1: TPIDR_EL1 + REG_SCXTNUM_EL21 =50823 /* 50823 */, // S3_0_c13_c0_7 at min EL1: SCXTNUM_EL21 + REG_SCXTNUM_EL1 =50823 /* 50823 */, + REG_REDIR_CNTKCTL_EL1 =50952 /* 50952 */, // S3_0_c14_c1_0 at min EL1: REDIR_CNTKCTL_EL1 + REG_CNTKCTL_EL1 =50952 /* 50952 */, + REG_HID0 =51072 /* 51072 */, // S3_0_c15_c0_0 at min EL1: HID0 + REG_HID25 =51074 /* 51074 */, // S3_0_c15_c0_2 at min EL1: HID25 + REG_HID26 =51075 /* 51075 */, // S3_0_c15_c0_3 at min EL1: HID26 + REG_HID27 =51076 /* 51076 */, // S3_0_c15_c0_4 at min EL1: HID27 + REG_HID28 =51077 /* 51077 */, // S3_0_c15_c0_5 at min EL1: HID28 + REG_HID29 =51078 /* 51078 */, // S3_0_c15_c0_6 at min EL1: HID29 + REG_HID34 =51079 /* 51079 */, // S3_0_c15_c0_7 at min EL1: HID34 + REG_HID1 =51080 /* 51080 */, // S3_0_c15_c1_0 at min EL1: HID1 + REG_HID21 =51083 /* 51083 */, // S3_0_c15_c1_3 at min EL1: HID21 + REG_BIUVCSCUPCMDCRD =51084 /* 51084 */, // S3_0_c15_c1_4 at min EL1: BiuVCSCUpCmdCrd + REG_BIUVCSCUPDATCRD =51085 /* 51085 */, // S3_0_c15_c1_5 at min EL1: BiuVCSCUpDatCrd + REG_HID2 =51088 /* 51088 */, // S3_0_c15_c2_0 at min EL1: HID2 + REG_HID30 =51091 /* 51091 */, // S3_0_c15_c2_3 at min EL1: HID30 + REG_HID31 =51092 /* 51092 */, // S3_0_c15_c2_4 at min EL1: HID31 + REG_HID32 =51093 /* 51093 */, // S3_0_c15_c2_5 at min EL1: HID32 + REG_HID33 =51095 /* 51095 */, // S3_0_c15_c2_7 at min EL1: HID33 + REG_HID3 =51096 /* 51096 */, // S3_0_c15_c3_0 at min EL1: HID3 + REG_BIUVCSCUPCMDCRDC2 =51098 /* 51098 */, // S3_0_c15_c3_2 at min EL1: BiuVCSCUpCmdCrdC2 + REG_BIUVCSCUPDATCRDC2 =51099 /* 51099 */, // S3_0_c15_c3_3 at min EL1: BiuVCSCUpDatCrdC2 + REG_HID4 =51104 /* 51104 */, // S3_0_c15_c4_0 at min EL1: HID4 + REG_HID5 =51112 /* 51112 */, // S3_0_c15_c5_0 at min EL1: HID5 + REG_HID6 =51120 /* 51120 */, // S3_0_c15_c6_0 at min EL1: HID6 + REG_HID7 =51128 /* 51128 */, // S3_0_c15_c7_0 at min EL1: HID7 + REG_HID8 =51136 /* 51136 */, // S3_0_c15_c8_0 at min EL1: HID8 + REG_HID9 =51144 /* 51144 */, // S3_0_c15_c9_0 at min EL1: HID9 + REG_HID10 =51152 /* 51152 */, // S3_0_c15_c10_0 at min EL1: HID10 + REG_BLOCK_CMAINT_CFG =51154 /* 51154 */, // S3_0_c15_c10_2 at min EL1: BLOCK_CMAINT_CFG + REG_HID11 =51160 /* 51160 */, // S3_0_c15_c11_0 at min EL1: HID11 + REG_HID18 =51162 /* 51162 */, // S3_0_c15_c11_2 at min EL1: HID18 + REG_HID36 =51164 /* 51164 */, // S3_0_c15_c11_4 at min EL1: HID36 + REG_HID37 =51165 /* 51165 */, // S3_0_c15_c11_5 at min EL1: HID37 + REG_HID12 =51168 /* 51168 */, // S3_0_c15_c12_0 at min EL1: HID12 + REG_HID15 =51169 /* 51169 */, // S3_0_c15_c12_1 at min EL1: HID15 + REG_HID19 =51170 /* 51170 */, // S3_0_c15_c12_2 at min EL1: HID19 + REG_BIU_TLIMIT =51176 /* 51176 */, // S3_0_c15_c13_0 at min EL1: BIU_TLIMIT + REG_HID13 =51184 /* 51184 */, // S3_0_c15_c14_0 at min EL1: HID13 + REG_HID_RCTX_G0CTL =51186 /* 51186 */, // S3_0_c15_c14_2 at min EL1: HID_RCTX_G0CTL + REG_HID_RCTX_G1CTL =51187 /* 51187 */, // S3_0_c15_c14_3 at min EL1: HID_RCTX_G1CTL + REG_HID14 =51192 /* 51192 */, // S3_0_c15_c15_0 at min EL1: HID14 + REG_HID16 =51194 /* 51194 */, // S3_0_c15_c15_2 at min EL1: HID16 + REG_LLC_WRR2 =51195 /* 51195 */, // S3_0_c15_c15_3 at min EL1: LLC_WRR2 + REG_BIU_AFI_CFG =51196 /* 51196 */, // S3_0_c15_c15_4 at min EL1: BIU_AFI_CFG + REG_HID17 =51197 /* 51197 */, // S3_0_c15_c15_5 at min EL1: HID17 + REG_HID24 =51198 /* 51198 */, // S3_0_c15_c15_6 at min EL1: HID24 + REG_HID35 =51199 /* 51199 */, // S3_0_c15_c15_7 at min EL1: HID35 + REG_CCSIDRPL1_I_EL1 =51200 /* 51200 */, // S3_1_c0_c0_0 at min EL1: CCSIDRPL1_I_EL1 + REG_CLIDR_EL1 =51201 /* 51201 */, // S3_1_c0_c0_1 at min EL1: CLIDR_EL1 + REG_SMIDR_EL1 =51206 /* 51206 */, // S3_1_c0_c0_6 at min EL1: SMIDR_EL1 + REG_AIDR_EL1 =51207 /* 51207 */, // S3_1_c0_c0_7 at min EL1: AIDR_EL1 + REG_PMCR0_EL1 =53120 /* 53120 */, // S3_1_c15_c0_0 at min EL1: PMCR0_EL1 + REG_APPL_CONTEXTPTR =53121 /* 53121 */, // S3_1_c15_c0_1 at min EL1: APPL_CONTEXTPTR + REG_LD_LATPROF_CTL_EL21 =53122 /* 53122 */, // S3_1_c15_c0_2 at min EL1: LD_LATPROF_CTL_EL21 + REG_AON_CPU_MSTALL_CTL01_EL1 =53123 /* 53123 */, // S3_1_c15_c0_3 at min EL1: AON_CPU_MSTALL_CTL01_EL1 + REG_PM_MEMFLT_CTL23_EL1 =53124 /* 53124 */, // S3_1_c15_c0_4 at min EL1: PM_MEMFLT_CTL23_EL1 + REG_REDIR_ACNTV_CTL_EL0 =53125 /* 53125 */, // S3_1_c15_c0_5 at min EL1: REDIR_ACNTV_CTL_EL0 + REG_LCL_ACNTVCTSS_NOREDIR_EL0 =53126 /* 53126 */, // S3_1_c15_c0_6 at min EL1: LCL_ACNTVCTSS_NOREDIR_EL0 + REG_PMCR1_EL21 =53128 /* 53128 */, // S3_1_c15_c1_0 at min EL1: PMCR1_EL21 + REG_LD_LATPROF_CTR_EL1 =53130 /* 53130 */, // S3_1_c15_c1_2 at min EL1: LD_LATPROF_CTR_EL1 + REG_AON_CPU_MSTALL_CTL23_EL1 =53131 /* 53131 */, // S3_1_c15_c1_3 at min EL1: AON_CPU_MSTALL_CTL23_EL1 + REG_PM_MEMFLT_CTL45_EL1 =53132 /* 53132 */, // S3_1_c15_c1_4 at min EL1: PM_MEMFLT_CTL45_EL1 + REG_AGTCNTRDIR_EL21 =53133 /* 53133 */, // S3_1_c15_c1_5 at min EL1: AGTCNTRDIR_EL21 + REG_AGTCNTKCTL_NOREDIR_EL1 =53134 /* 53134 */, // S3_1_c15_c1_6 at min EL1: AGTCNTKCTL_NOREDIR_EL1 + REG_PMCR2_EL1 =53136 /* 53136 */, // S3_1_c15_c2_0 at min EL1: PMCR2_EL1 + REG_LD_LATPROF_STS_EL1 =53138 /* 53138 */, // S3_1_c15_c2_2 at min EL1: LD_LATPROF_STS_EL1 + REG_AON_CPU_MSTALL_CTL45_EL1 =53139 /* 53139 */, // S3_1_c15_c2_3 at min EL1: AON_CPU_MSTALL_CTL45_EL1 + REG_REDIR_ACNTHP_CVAL_EL2 =53140 /* 53140 */, // S3_1_c15_c2_4 at min EL2: REDIR_ACNTHP_CVAL_EL2 + REG_LCL_CNTVCT_NOREDIR_EL0 =53141 /* 53141 */, // S3_1_c15_c2_5 at min EL1: LCL_CNTVCT_NOREDIR_EL0 + REG_AGTCNTP_CVAL_NOREDIR_EL0 =53142 /* 53142 */, // S3_1_c15_c2_6 at min EL1: AGTCNTP_CVAL_NOREDIR_EL0 + REG_PMCR3_EL1 =53144 /* 53144 */, // S3_1_c15_c3_0 at min EL1: PMCR3_EL1 + REG_LD_LATPROF_INF_EL1 =53146 /* 53146 */, // S3_1_c15_c3_2 at min EL1: LD_LATPROF_INF_EL1 + REG_AON_CPU_MSTALL_CTL67_EL1 =53147 /* 53147 */, // S3_1_c15_c3_3 at min EL1: AON_CPU_MSTALL_CTL67_EL1 + REG_REDIR_ACNTHP_TVAL_EL2 =53148 /* 53148 */, // S3_1_c15_c3_4 at min EL2: REDIR_ACNTHP_TVAL_EL2 + REG_LCL_CNTPCTSS_NOREDIR_EL0 =53149 /* 53149 */, // S3_1_c15_c3_5 at min EL1: LCL_CNTPCTSS_NOREDIR_EL0 + REG_AGTCNTP_TVAL_NOREDIR_EL0 =53150 /* 53150 */, // S3_1_c15_c3_6 at min EL1: AGTCNTP_TVAL_NOREDIR_EL0 + REG_PMCR4_EL1 =53152 /* 53152 */, // S3_1_c15_c4_0 at min EL1: PMCR4_EL1 + REG_LD_LATPROF_CTL_EL2 =53154 /* 53154 */, // S3_1_c15_c4_2 at min EL2: LD_LATPROF_CTL_EL2 + REG_AON_CPU_MEMFLT_CTL01_EL1 =53155 /* 53155 */, // S3_1_c15_c4_3 at min EL1: AON_CPU_MEMFLT_CTL01_EL1 + REG_REDIR_ACNTHP_CTL_EL2 =53156 /* 53156 */, // S3_1_c15_c4_4 at min EL2: REDIR_ACNTHP_CTL_EL2 + REG_LCL_CNTVCTSS_NOREDIR_EL0 =53157 /* 53157 */, // S3_1_c15_c4_5 at min EL1: LCL_CNTVCTSS_NOREDIR_EL0 + REG_AGTCNTP_CTL_NOREDIR_EL0 =53158 /* 53158 */, // S3_1_c15_c4_6 at min EL1: AGTCNTP_CTL_NOREDIR_EL0 + REG_PMESR0_EL1 =53160 /* 53160 */, // S3_1_c15_c5_0 at min EL1: PMESR0_EL1 + REG_LD_LATPROF_CMD_EL1 =53162 /* 53162 */, // S3_1_c15_c5_2 at min EL1: LD_LATPROF_CMD_EL1 + REG_AON_CPU_MEMFLT_CTL23_EL1 =53163 /* 53163 */, // S3_1_c15_c5_3 at min EL1: AON_CPU_MEMFLT_CTL23_EL1 + REG_REDIR_ACNTHV_CVAL_EL2 =53164 /* 53164 */, // S3_1_c15_c5_4 at min EL2: REDIR_ACNTHV_CVAL_EL2 + REG_AGTCNTV_CVAL_NOREDIR_EL0 =53166 /* 53166 */, // S3_1_c15_c5_6 at min EL1: AGTCNTV_CVAL_NOREDIR_EL0 + REG_PMESR1_EL1 =53168 /* 53168 */, // S3_1_c15_c6_0 at min EL1: PMESR1_EL1 + REG_PMCR1_EL2 =53170 /* 53170 */, // S3_1_c15_c6_2 at min EL2: PMCR1_EL2 + REG_AON_CPU_MEMFLT_CTL45_EL1 =53171 /* 53171 */, // S3_1_c15_c6_3 at min EL1: AON_CPU_MEMFLT_CTL45_EL1 + REG_REDIR_ACNTHV_TVAL_EL2 =53172 /* 53172 */, // S3_1_c15_c6_4 at min EL2: REDIR_ACNTHV_TVAL_EL2 + REG_CNTKCTL_NOREDIR_EL1 =53173 /* 53173 */, // S3_1_c15_c6_5 at min EL1: CNTKCTL_NOREDIR_EL1 + REG_AGTCNTV_TVAL_NOREDIR_EL0 =53174 /* 53174 */, // S3_1_c15_c6_6 at min EL1: AGTCNTV_TVAL_NOREDIR_EL0 + REG_OPMAT0_EL1 =53176 /* 53176 */, // S3_1_c15_c7_0 at min EL1: OPMAT0_EL1 + REG_PMCR1_EL12 =53178 /* 53178 */, // S3_1_c15_c7_2 at min EL2: PMCR1_EL12 + REG_AON_CPU_MEMFLT_CTL67_EL1 =53179 /* 53179 */, // S3_1_c15_c7_3 at min EL1: AON_CPU_MEMFLT_CTL67_EL1 + REG_REDIR_ACNTHV_CTL_EL2 =53180 /* 53180 */, // S3_1_c15_c7_4 at min EL2: REDIR_ACNTHV_CTL_EL2 + REG_CNTP_CVAL_NOREDIR_EL0 =53181 /* 53181 */, // S3_1_c15_c7_5 at min EL1: CNTP_CVAL_NOREDIR_EL0 + REG_AGTCNTV_CTL_NOREDIR_EL0 =53182 /* 53182 */, // S3_1_c15_c7_6 at min EL1: AGTCNTV_CTL_NOREDIR_EL0 + REG_OPMAT1_EL1 =53184 /* 53184 */, // S3_1_c15_c8_0 at min EL1: OPMAT1_EL1 + REG_PMCR1_GL12 =53186 /* 53186 */, // S3_1_c15_c8_2 at min EL2: PMCR1_GL12 + REG_AON_CPU_MSTALL_CTR0_EL1 =53187 /* 53187 */, // S3_1_c15_c8_3 at min EL1: AON_CPU_MSTALL_CTR0_EL1 + REG_REDIR_ACNTFRQ_EL0 =53188 /* 53188 */, // S3_1_c15_c8_4 at min EL1: REDIR_ACNTFRQ_EL0 + REG_CNTP_TVAL_NOREDIR_EL0 =53189 /* 53189 */, // S3_1_c15_c8_5 at min EL1: CNTP_TVAL_NOREDIR_EL0 + REG_LCL_CNTPCT_NOREDIR_EL0 =53190 /* 53190 */, // S3_1_c15_c8_6 at min EL1: LCL_CNTPCT_NOREDIR_EL0 + REG_OPMSK0_EL1 =53192 /* 53192 */, // S3_1_c15_c9_0 at min EL1: OPMSK0_EL1 + REG_LD_LATPROF_CTL_EL12 =53194 /* 53194 */, // S3_1_c15_c9_2 at min EL2: LD_LATPROF_CTL_EL12 + REG_AON_CPU_MSTALL_CTR1_EL1 =53195 /* 53195 */, // S3_1_c15_c9_3 at min EL1: AON_CPU_MSTALL_CTR1_EL1 + REG_AGTCNTVOFF_EL2 =53196 /* 53196 */, // S3_1_c15_c9_4 at min EL2: AGTCNTVOFF_EL2 + REG_CNTP_CTL_NOREDIR_EL0 =53197 /* 53197 */, // S3_1_c15_c9_5 at min EL1: CNTP_CTL_NOREDIR_EL0 + REG_CNTV_CTL_NOREDIR_EL0 =53198 /* 53198 */, // S3_1_c15_c9_6 at min EL1: CNTV_CTL_NOREDIR_EL0 + REG_OPMSK1_EL1 =53200 /* 53200 */, // S3_1_c15_c10_0 at min EL1: OPMSK1_EL1 + REG_LD_LATPROF_INF_EL2 =53202 /* 53202 */, // S3_1_c15_c10_2 at min EL2: LD_LATPROF_INF_EL2 + REG_AON_CPU_MSTALL_CTR2_EL1 =53203 /* 53203 */, // S3_1_c15_c10_3 at min EL1: AON_CPU_MSTALL_CTR2_EL1 + REG_REDIR_ACNTP_CVAL_EL0 =53204 /* 53204 */, // S3_1_c15_c10_4 at min EL1: REDIR_ACNTP_CVAL_EL0 + REG_CNTV_CVAL_NOREDIR_EL0 =53205 /* 53205 */, // S3_1_c15_c10_5 at min EL1: CNTV_CVAL_NOREDIR_EL0 + REG_LCL_ACNTPCT_NOREDIR_EL0 =53206 /* 53206 */, // S3_1_c15_c10_6 at min EL1: LCL_ACNTPCT_NOREDIR_EL0 + REG_AON_CPU_MSTALL_CTR3_EL1 =53211 /* 53211 */, // S3_1_c15_c11_3 at min EL1: AON_CPU_MSTALL_CTR3_EL1 + REG_REDIR_ACNTP_TVAL_EL0 =53212 /* 53212 */, // S3_1_c15_c11_4 at min EL1: REDIR_ACNTP_TVAL_EL0 + REG_CNTV_TVAL_NOREDIR_EL0 =53213 /* 53213 */, // S3_1_c15_c11_5 at min EL1: CNTV_TVAL_NOREDIR_EL0 + REG_VMSA_HV_LOCK_EL2 =53214 /* 53214 */, // S3_1_c15_c11_6 at min EL2: VMSA_HV_LOCK_EL2 + REG_PMSWCTRL_EL1 =53216 /* 53216 */, // S3_1_c15_c12_0 at min EL1: PMSWCTRL_EL1 + REG_PMCR5_EL0 =53217 /* 53217 */, // S3_1_c15_c12_1 at min EL1: PMCR5_EL0 + REG_AON_CPU_MSTALL_CTR4_EL1 =53219 /* 53219 */, // S3_1_c15_c12_3 at min EL1: AON_CPU_MSTALL_CTR4_EL1 + REG_PMCOMPARE0_EL1 =53220 /* 53220 */, // S3_1_c15_c12_4 at min EL1: PMCompare0_EL1 + REG_PMCOMPARE1_EL1 =53221 /* 53221 */, // S3_1_c15_c12_5 at min EL1: PMCompare1_EL1 + REG_VMSA_NV_LOCK_EL2 =53222 /* 53222 */, // S3_1_c15_c12_6 at min EL2: VMSA_NV_LOCK_EL2 + REG_PMSR_EL1 =53224 /* 53224 */, // S3_1_c15_c13_0 at min EL1: PMSR_EL1 + REG_AON_CPU_MSTALL_CTR5_EL1 =53227 /* 53227 */, // S3_1_c15_c13_3 at min EL1: AON_CPU_MSTALL_CTR5_EL1 + REG_REDIR_ACNTP_CTL_EL0 =53228 /* 53228 */, // S3_1_c15_c13_4 at min EL1: REDIR_ACNTP_CTL_EL0 + REG_PMCOMPARE5_EL1 =53229 /* 53229 */, // S3_1_c15_c13_5 at min EL1: PMCompare5_EL1 + REG_PMCOMPARE6_EL1 =53230 /* 53230 */, // S3_1_c15_c13_6 at min EL1: PMCompare6_EL1 + REG_PMCOMPARE7_EL1 =53231 /* 53231 */, // S3_1_c15_c13_7 at min EL1: PMCompare7_EL1 + REG_PMCR_BVRNG4_EL1 =53232 /* 53232 */, // S3_1_c15_c14_0 at min EL1: PMCR_BVRNG4_EL1 + REG_PM_PMI_PC =53233 /* 53233 */, // S3_1_c15_c14_1 at min EL1: PM_PMI_PC + REG_AON_CPU_MSTALL_CTR6_EL1 =53235 /* 53235 */, // S3_1_c15_c14_3 at min EL1: AON_CPU_MSTALL_CTR6_EL1 + REG_REDIR_ACNTV_CVAL_EL0 =53236 /* 53236 */, // S3_1_c15_c14_4 at min EL1: REDIR_ACNTV_CVAL_EL0 + REG_LCL_ACNTVCT_NOREDIR_EL0 =53237 /* 53237 */, // S3_1_c15_c14_5 at min EL1: LCL_ACNTVCT_NOREDIR_EL0 + REG_PMCR_BVRNG5_EL1 =53240 /* 53240 */, // S3_1_c15_c15_0 at min EL1: PMCR_BVRNG5_EL1 + REG_AON_CPU_MSTALL_CTR7_EL1 =53243 /* 53243 */, // S3_1_c15_c15_3 at min EL1: AON_CPU_MSTALL_CTR7_EL1 + REG_REDIR_ACNTV_TVAL_EL0 =53244 /* 53244 */, // S3_1_c15_c15_4 at min EL1: REDIR_ACNTV_TVAL_EL0 + REG_LCL_ACNTPCTSS_NOREDIR_EL0 =53245 /* 53245 */, // S3_1_c15_c15_5 at min EL1: LCL_ACNTPCTSS_NOREDIR_EL0 + REG_CSSELR_EL1 =53248 /* 53248 */, // S3_2_c0_c0_0 at min EL1: CSSELR_EL1 + REG_PMC0 =55168 /* 55168 */, // S3_2_c15_c0_0 at min EL1: PMC0 + REG_UPMCFILTER0 =55169 /* 55169 */, // S3_2_c15_c0_1 at min EL1: UPMCFILTER0 + REG_UPMCFILTER1 =55170 /* 55170 */, // S3_2_c15_c0_2 at min EL1: UPMCFILTER1 + REG_UPMCFILTER2 =55171 /* 55171 */, // S3_2_c15_c0_3 at min EL1: UPMCFILTER2 + REG_UPMCFILTER3 =55172 /* 55172 */, // S3_2_c15_c0_4 at min EL1: UPMCFILTER3 + REG_UPMCFILTER4 =55173 /* 55173 */, // S3_2_c15_c0_5 at min EL1: UPMCFILTER4 + REG_UPMCFILTER5 =55174 /* 55174 */, // S3_2_c15_c0_6 at min EL1: UPMCFILTER5 + REG_UPMCFILTER6 =55175 /* 55175 */, // S3_2_c15_c0_7 at min EL1: UPMCFILTER6 + REG_PMC1 =55176 /* 55176 */, // S3_2_c15_c1_0 at min EL1: PMC1 + REG_UPMCFILTER7 =55177 /* 55177 */, // S3_2_c15_c1_1 at min EL1: UPMCFILTER7 + REG_PMC2 =55184 /* 55184 */, // S3_2_c15_c2_0 at min EL1: PMC2 + REG_PMC3 =55192 /* 55192 */, // S3_2_c15_c3_0 at min EL1: PMC3 + REG_PMC4 =55200 /* 55200 */, // S3_2_c15_c4_0 at min EL1: PMC4 + REG_PMC5 =55208 /* 55208 */, // S3_2_c15_c5_0 at min EL1: PMC5 + REG_PMC6 =55216 /* 55216 */, // S3_2_c15_c6_0 at min EL1: PMC6 + REG_PMC7 =55224 /* 55224 */, // S3_2_c15_c7_0 at min EL1: PMC7 + REG_PMC8 =55240 /* 55240 */, // S3_2_c15_c9_0 at min EL1: PMC8 + REG_PMC9 =55248 /* 55248 */, // S3_2_c15_c10_0 at min EL1: PMC9 + REG_PMTRHLD6_EL1 =55264 /* 55264 */, // S3_2_c15_c12_0 at min EL1: PMTRHLD6_EL1 + REG_PMTRHLD4_EL1 =55272 /* 55272 */, // S3_2_c15_c13_0 at min EL1: PMTRHLD4_EL1 + REG_PMTRHLD2_EL1 =55280 /* 55280 */, // S3_2_c15_c14_0 at min EL1: PMTRHLD2_EL1 + REG_PMMMAP_EL1 =55288 /* 55288 */, // S3_2_c15_c15_0 at min EL1: PMMMAP_EL1 + REG_CTR_EL0 =55297 /* 55297 */, // S3_3_c0_c0_1 at min EL1: CTR_EL0 + REG_DCZID_EL0 =55303 /* 55303 */, // S3_3_c0_c0_7 at min EL1: DCZID_EL0 + REG_NZCV =55824 /* 55824 */, // S3_3_c4_c2_0 at min EL1: NZCV + REG_DAIF =55825 /* 55825 */, // S3_3_c4_c2_1 at min EL1: DAIF + REG_DAIFSET =55825 /* 55825 */, + REG_SVCR =55826 /* 55826 */, // S3_3_c4_c2_2 at min EL1: SVCR + REG_DIT =55829 /* 55829 */, // S3_3_c4_c2_5 at min EL1: DIT + REG_SSBS =55830 /* 55830 */, + REG_TCO =55831 /* 55831 */, + REG_FPCR =55840 /* 55840 */, // S3_3_c4_c4_0 at min EL1: FPCR + REG_FPSR =55841 /* 55841 */, // S3_3_c4_c4_1 at min EL1: FPSR + REG_DSPSR_EL0 =55848 /* 55848 */, // S3_3_c4_c5_0 at min EL1: DSPSR_EL0 + REG_DLR_EL0 =55849 /* 55849 */, // S3_3_c4_c5_1 at min EL1: DLR_EL0 + REG_PMCR_EL0 =56544 /* 56544 */, + REG_PMCNTENSET_EL0 =56545 /* 56545 */, + REG_PMCNTENCLR_EL0 =56546 /* 56546 */, + REG_PMOVSCLR_EL0 =56547 /* 56547 */, + REG_PMSWINC_EL0 =56548 /* 56548 */, + REG_PMSELR_EL0 =56549 /* 56549 */, + REG_PMCCNTR_EL0 =56552 /* 56552 */, + REG_PMXEVTYPER_EL0 =56553 /* 56553 */, + REG_PMXEVCNTR_EL0 =56554 /* 56554 */, + REG_DAIFCLR =56557 /* 56557 */, + REG_PMUSERENR_EL0 =56560 /* 56560 */, + REG_PMOVSSET_EL0 =56563 /* 56563 */, + REG_TPIDR_EL0 =56962 /* 56962 */, // S3_3_c13_c0_2 at min EL1: TPIDR_EL0 + REG_TPIDRRO_EL0 =56963 /* 56963 */, // S3_3_c13_c0_3 at min EL1: TPIDRRO_EL0 + REG_TPIDR2_EL0 =56965 /* 56965 */, // S3_3_c13_c0_5 at min EL1: TPIDR2_EL0 + REG_SCXTNUM_EL0 =56967 /* 56967 */, // S3_3_c13_c0_7 at min EL1: SCXTNUM_EL0 + REG_AMCR_EL0 =56976 /* 56976 */, + REG_AMUSERENR_EL0 =56979 /* 56979 */, + REG_AMCNTENCLR0_EL0 =56980 /* 56980 */, + REG_AMCNTENSET0_EL0 =56981 /* 56981 */, + REG_AMCNTENCLR1_EL0 =56984 /* 56984 */, + REG_AMCNTENSET1_EL0 =56985 /* 56985 */, + REG_AMEVCNTR00_EL0 =56992 /* 56992 */, + REG_AMEVCNTR01_EL0 =56993 /* 56993 */, + REG_AMEVCNTR02_EL0 =56994 /* 56994 */, + REG_AMEVCNTR03_EL0 =56995 /* 56995 */, + REG_AMEVCNTR10_EL0 =57056 /* 57056 */, + REG_AMEVCNTR11_EL0 =57057 /* 57057 */, + REG_AMEVCNTR12_EL0 =57058 /* 57058 */, + REG_AMEVCNTR13_EL0 =57059 /* 57059 */, + REG_AMEVCNTR14_EL0 =57060 /* 57060 */, + REG_AMEVCNTR15_EL0 =57061 /* 57061 */, + REG_AMEVCNTR16_EL0 =57062 /* 57062 */, + REG_AMEVCNTR17_EL0 =57063 /* 57063 */, + REG_AMEVCNTR18_EL0 =57064 /* 57064 */, + REG_AMEVCNTR19_EL0 =57065 /* 57065 */, + REG_AMEVCNTR110_EL0 =57066 /* 57066 */, + REG_AMEVCNTR111_EL0 =57067 /* 57067 */, + REG_AMEVCNTR112_EL0 =57068 /* 57068 */, + REG_AMEVCNTR113_EL0 =57069 /* 57069 */, + REG_AMEVCNTR114_EL0 =57070 /* 57070 */, + REG_AMEVCNTR115_EL0 =57071 /* 57071 */, + REG_AMEVTYPER10_EL0 =57072 /* 57072 */, + REG_AMEVTYPER11_EL0 =57073 /* 57073 */, + REG_AMEVTYPER12_EL0 =57074 /* 57074 */, + REG_AMEVTYPER13_EL0 =57075 /* 57075 */, + REG_AMEVTYPER14_EL0 =57076 /* 57076 */, + REG_AMEVTYPER15_EL0 =57077 /* 57077 */, + REG_AMEVTYPER16_EL0 =57078 /* 57078 */, + REG_AMEVTYPER17_EL0 =57079 /* 57079 */, + REG_AMEVTYPER18_EL0 =57080 /* 57080 */, + REG_AMEVTYPER19_EL0 =57081 /* 57081 */, + REG_AMEVTYPER110_EL0 =57082 /* 57082 */, + REG_AMEVTYPER111_EL0 =57083 /* 57083 */, + REG_AMEVTYPER112_EL0 =57084 /* 57084 */, + REG_AMEVTYPER113_EL0 =57085 /* 57085 */, + REG_AMEVTYPER114_EL0 =57086 /* 57086 */, + REG_AMEVTYPER115_EL0 =57087 /* 57087 */, + REG_REDIR_CNTFRQ_EL0 =57088 /* 57088 */, // S3_3_c14_c0_0 at min EL1: REDIR_CNTFRQ_EL0 + REG_CNTFRQ_EL0 =57088 /* 57088 */, + REG_REDIR_LCL_CNTPCT_EL0 =57089 /* 57089 */, // S3_3_c14_c0_1 at min EL1: REDIR_LCL_CNTPCT_EL0 + REG_CNTPCT_EL0 =57089 /* 57089 */, + REG_REDIR_LCL_CNTVCT_EL0 =57090 /* 57090 */, // S3_3_c14_c0_2 at min EL1: REDIR_LCL_CNTVCT_EL0 + REG_REDIR_LCL_CNTPCTSS_EL0 =57093 /* 57093 */, // S3_3_c14_c0_5 at min EL1: REDIR_LCL_CNTPCTSS_EL0 + REG_REDIR_LCL_CNTVCTSS_EL0 =57094 /* 57094 */, // S3_3_c14_c0_6 at min EL1: REDIR_LCL_CNTVCTSS_EL0 + REG_REDIR_CNTP_TVAL_EL0 =57104 /* 57104 */, // S3_3_c14_c2_0 at min EL1: REDIR_CNTP_TVAL_EL0 + REG_CNTP_TVAL_EL0 =57104 /* 57104 */, + REG_REDIR_CNTP_CTL_EL0 =57105 /* 57105 */, // S3_3_c14_c2_1 at min EL1: REDIR_CNTP_CTL_EL0 + REG_CNTP_CTL_EL0 =57105 /* 57105 */, + REG_REDIR_CNTP_CVAL_EL0 =57106 /* 57106 */, // S3_3_c14_c2_2 at min EL1: REDIR_CNTP_CVAL_EL0 + REG_CNTP_CVAL_EL0 =57106 /* 57106 */, + REG_REDIR_CNTV_TVAL_EL0 =57112 /* 57112 */, // S3_3_c14_c3_0 at min EL1: REDIR_CNTV_TVAL_EL0 + REG_CNTV_TVAL_EL0 =57112 /* 57112 */, + REG_REDIR_CNTV_CTL_EL0 =57113 /* 57113 */, // S3_3_c14_c3_1 at min EL1: REDIR_CNTV_CTL_EL0 + REG_CNTV_CTL_EL0 =57113 /* 57113 */, + REG_REDIR_CNTV_CVAL_EL0 =57114 /* 57114 */, // S3_3_c14_c3_2 at min EL1: REDIR_CNTV_CVAL_EL0 + REG_CNTV_CVAL_EL0 =57114 /* 57114 */, + REG_PMEVCNTR0_EL0 =57152 /* 57152 */, + REG_PMEVCNTR1_EL0 =57153 /* 57153 */, + REG_PMEVCNTR2_EL0 =57154 /* 57154 */, + REG_PMEVCNTR3_EL0 =57155 /* 57155 */, + REG_PMEVCNTR4_EL0 =57156 /* 57156 */, + REG_PMEVCNTR5_EL0 =57157 /* 57157 */, + REG_PMEVCNTR6_EL0 =57158 /* 57158 */, + REG_PMEVCNTR7_EL0 =57159 /* 57159 */, + REG_PMEVCNTR8_EL0 =57160 /* 57160 */, + REG_PMEVCNTR9_EL0 =57161 /* 57161 */, + REG_PMEVCNTR10_EL0 =57162 /* 57162 */, + REG_PMEVCNTR11_EL0 =57163 /* 57163 */, + REG_PMEVCNTR12_EL0 =57164 /* 57164 */, + REG_PMEVCNTR13_EL0 =57165 /* 57165 */, + REG_PMEVCNTR14_EL0 =57166 /* 57166 */, + REG_PMEVCNTR15_EL0 =57167 /* 57167 */, + REG_PMEVCNTR16_EL0 =57168 /* 57168 */, + REG_PMEVCNTR17_EL0 =57169 /* 57169 */, + REG_PMEVCNTR18_EL0 =57170 /* 57170 */, + REG_PMEVCNTR19_EL0 =57171 /* 57171 */, + REG_PMEVCNTR20_EL0 =57172 /* 57172 */, + REG_PMEVCNTR21_EL0 =57173 /* 57173 */, + REG_PMEVCNTR22_EL0 =57174 /* 57174 */, + REG_PMEVCNTR23_EL0 =57175 /* 57175 */, + REG_PMEVCNTR24_EL0 =57176 /* 57176 */, + REG_PMEVCNTR25_EL0 =57177 /* 57177 */, + REG_PMEVCNTR26_EL0 =57178 /* 57178 */, + REG_PMEVCNTR27_EL0 =57179 /* 57179 */, + REG_PMEVCNTR28_EL0 =57180 /* 57180 */, + REG_PMEVCNTR29_EL0 =57181 /* 57181 */, + REG_PMEVCNTR30_EL0 =57182 /* 57182 */, + REG_PMEVTYPER0_EL0 =57184 /* 57184 */, + REG_PMEVTYPER1_EL0 =57185 /* 57185 */, + REG_PMEVTYPER2_EL0 =57186 /* 57186 */, + REG_PMEVTYPER3_EL0 =57187 /* 57187 */, + REG_PMEVTYPER4_EL0 =57188 /* 57188 */, + REG_PMEVTYPER5_EL0 =57189 /* 57189 */, + REG_PMEVTYPER6_EL0 =57190 /* 57190 */, + REG_PMEVTYPER7_EL0 =57191 /* 57191 */, + REG_PMEVTYPER8_EL0 =57192 /* 57192 */, + REG_PMEVTYPER9_EL0 =57193 /* 57193 */, + REG_PMEVTYPER10_EL0 =57194 /* 57194 */, + REG_PMEVTYPER11_EL0 =57195 /* 57195 */, + REG_PMEVTYPER12_EL0 =57196 /* 57196 */, + REG_PMEVTYPER13_EL0 =57197 /* 57197 */, + REG_PMEVTYPER14_EL0 =57198 /* 57198 */, + REG_PMEVTYPER15_EL0 =57199 /* 57199 */, + REG_PMEVTYPER16_EL0 =57200 /* 57200 */, + REG_PMEVTYPER17_EL0 =57201 /* 57201 */, + REG_PMEVTYPER18_EL0 =57202 /* 57202 */, + REG_PMEVTYPER19_EL0 =57203 /* 57203 */, + REG_PMEVTYPER20_EL0 =57204 /* 57204 */, + REG_PMEVTYPER21_EL0 =57205 /* 57205 */, + REG_PMEVTYPER22_EL0 =57206 /* 57206 */, + REG_PMEVTYPER23_EL0 =57207 /* 57207 */, + REG_PMEVTYPER24_EL0 =57208 /* 57208 */, + REG_PMEVTYPER25_EL0 =57209 /* 57209 */, + REG_PMEVTYPER26_EL0 =57210 /* 57210 */, + REG_PMEVTYPER27_EL0 =57211 /* 57211 */, + REG_PMEVTYPER28_EL0 =57212 /* 57212 */, + REG_PMEVTYPER29_EL0 =57213 /* 57213 */, + REG_PMEVTYPER30_EL0 =57214 /* 57214 */, + REG_PMCCFILTR_EL0 =57215 /* 57215 */, + REG_LSU_ERR_STS =57216 /* 57216 */, // S3_3_c15_c0_0 at min EL1: LSU_ERR_STS + REG_AFLATCTL1_EL1 =57220 /* 57220 */, // S3_3_c15_c0_4 at min EL1: AFLATCTL1_EL1 + REG_AFLATVALBIN0_EL1 =57221 /* 57221 */, // S3_3_c15_c0_5 at min EL1: AFLATVALBIN0_EL1 + REG_AFLATINFLO_EL1 =57222 /* 57222 */, // S3_3_c15_c0_6 at min EL1: AFLATINFLO_EL1 + REG_LSU_ERR_CTL =57224 /* 57224 */, // S3_3_c15_c1_0 at min EL1: LSU_ERR_CTL + REG_AFLATCTL2_EL1 =57228 /* 57228 */, // S3_3_c15_c1_4 at min EL1: AFLATCTL2_EL1 + REG_AFLATVALBIN1_EL1 =57229 /* 57229 */, // S3_3_c15_c1_5 at min EL1: AFLATVALBIN1_EL1 + REG_AFLATINFHI_EL1 =57230 /* 57230 */, // S3_3_c15_c1_6 at min EL1: AFLATINFHI_EL1 + REG_AFLATCTL3_EL1 =57236 /* 57236 */, // S3_3_c15_c2_4 at min EL1: AFLATCTL3_EL1 + REG_AFLATVALBIN2_EL1 =57237 /* 57237 */, // S3_3_c15_c2_5 at min EL1: AFLATVALBIN2_EL1 + REG_AFLATCTL4_EL1 =57244 /* 57244 */, // S3_3_c15_c3_4 at min EL1: AFLATCTL4_EL1 + REG_AFLATVALBIN3_EL1 =57245 /* 57245 */, // S3_3_c15_c3_5 at min EL1: AFLATVALBIN3_EL1 + REG_LLC_FILL_CTL =57248 /* 57248 */, // S3_3_c15_c4_0 at min EL1: LLC_FILL_CTL + REG_AFLATCTL5_LO_EL1 =57252 /* 57252 */, // S3_3_c15_c4_4 at min EL1: AFLATCTL5_LO_EL1 + REG_AFLATVALBIN4_EL1 =57253 /* 57253 */, // S3_3_c15_c4_5 at min EL1: AFLATVALBIN4_EL1 + REG_AFLATCTL5_HI_EL1 =57254 /* 57254 */, // S3_3_c15_c4_6 at min EL1: AFLATCTL5_HI_EL1 + REG_LLC_FILL_DAT =57256 /* 57256 */, // S3_3_c15_c5_0 at min EL1: LLC_FILL_DAT + REG_AFLATVALBIN5_EL1 =57261 /* 57261 */, // S3_3_c15_c5_5 at min EL1: AFLATVALBIN5_EL1 + REG_AFLATVALBIN6_EL1 =57269 /* 57269 */, // S3_3_c15_c6_5 at min EL1: AFLATVALBIN6_EL1 + REG_LLC_RAM_CONFIG =57272 /* 57272 */, // S3_3_c15_c7_0 at min EL1: LLC_RAM_CONFIG + REG_AFLATVALBIN7_EL1 =57277 /* 57277 */, // S3_3_c15_c7_5 at min EL1: AFLATVALBIN7_EL1 + REG_LLC_ERR_STS =57280 /* 57280 */, // S3_3_c15_c8_0 at min EL1: LLC_ERR_STS + REG_CMAINT_BCAST_LIST_0 =57281 /* 57281 */, // S3_3_c15_c8_1 at min EL1: CMAINT_BCAST_LIST_0 + REG_CMAINT_BCAST_LIST_1 =57282 /* 57282 */, // S3_3_c15_c8_2 at min EL1: CMAINT_BCAST_LIST_1 + REG_CMAINT_BCAST_CTL =57283 /* 57283 */, // S3_3_c15_c8_3 at min EL1: CMAINT_BCAST_CTL + REG_LLC_ERR_ADR =57288 /* 57288 */, // S3_3_c15_c9_0 at min EL1: LLC_ERR_ADR + REG_LLC_ERR_CTL =57289 /* 57289 */, // S3_3_c15_c9_1 at min EL1: LLC_ERR_CTL + REG_LLC_ERR_INJ =57290 /* 57290 */, // S3_3_c15_c9_2 at min EL1: LLC_ERR_INJ + REG_LLC_ERR_INF =57296 /* 57296 */, // S3_3_c15_c10_0 at min EL1: LLC_ERR_INF + REG_USERTAGSEL_EL1 =57297 /* 57297 */, // S3_3_c15_c10_1 at min EL1: USERTAGSEL_EL1 + REG_UUSERTAG_EL0 =57298 /* 57298 */, // S3_3_c15_c10_2 at min EL1: UUSERTAG_EL0 + REG_KUSERTAG_EL1 =57299 /* 57299 */, // S3_3_c15_c10_3 at min EL1: KUSERTAG_EL1 + REG_HUSERTAG_EL2 =57300 /* 57300 */, // S3_3_c15_c10_4 at min EL2: HUSERTAG_EL2 + REG_LLC_TRACE_CTL0 =57304 /* 57304 */, // S3_3_c15_c11_0 at min EL1: LLC_TRACE_CTL0 + REG_LLC_TRACE_CTL1 =57312 /* 57312 */, // S3_3_c15_c12_0 at min EL1: LLC_TRACE_CTL1 + REG_LLC_UP_REQ_VC =57320 /* 57320 */, // S3_3_c15_c13_0 at min EL1: LLC_UP_REQ_VC + REG_LLC_UP_REQ_VC_THRESH =57321 /* 57321 */, // S3_3_c15_c13_1 at min EL1: LLC_UP_REQ_VC_THRESH + REG_LLC_UP_REQ_VC_2 =57322 /* 57322 */, // S3_3_c15_c13_2 at min EL1: LLC_UP_REQ_VC_2 + REG_LLC_UP_REQ_VC_THRESH_2 =57323 /* 57323 */, // S3_3_c15_c13_3 at min EL1: LLC_UP_REQ_VC_THRESH_2 + REG_LLC_DRAM_HASH0 =57324 /* 57324 */, // S3_3_c15_c13_4 at min EL1: LLC_DRAM_HASH0 + REG_LLC_DRAM_HASH1 =57325 /* 57325 */, // S3_3_c15_c13_5 at min EL1: LLC_DRAM_HASH1 + REG_LLC_DRAM_HASH2 =57326 /* 57326 */, // S3_3_c15_c13_6 at min EL1: LLC_DRAM_HASH2 + REG_LLC_DRAM_HASH3 =57327 /* 57327 */, // S3_3_c15_c13_7 at min EL1: LLC_DRAM_HASH3 + REG_LLC_TRACE_CTL2 =57328 /* 57328 */, // S3_3_c15_c14_0 at min EL1: LLC_TRACE_CTL2 + REG_LLC_DRAM_HASH4 =57329 /* 57329 */, // S3_3_c15_c14_1 at min EL1: LLC_DRAM_HASH4 + REG_LLC_UP_REQ_VC_3 =57330 /* 57330 */, // S3_3_c15_c14_2 at min EL1: LLC_UP_REQ_VC_3 + REG_LLC_UP_REQ_VC_THRESH_3 =57331 /* 57331 */, // S3_3_c15_c14_3 at min EL1: LLC_UP_REQ_VC_THRESH_3 + REG_LLC_UP_REQ_VC_4 =57332 /* 57332 */, // S3_3_c15_c14_4 at min EL1: LLC_UP_REQ_VC_4 + REG_LLC_UP_REQ_VC_THRESH_4 =57333 /* 57333 */, // S3_3_c15_c14_5 at min EL1: LLC_UP_REQ_VC_THRESH_4 + REG_LLC_HASH0 =57336 /* 57336 */, // S3_3_c15_c15_0 at min EL1: LLC_HASH0 + REG_LLC_HASH1 =57337 /* 57337 */, // S3_3_c15_c15_1 at min EL1: LLC_HASH1 + REG_LLC_HASH2 =57338 /* 57338 */, // S3_3_c15_c15_2 at min EL1: LLC_HASH2 + REG_LLC_HASH3 =57339 /* 57339 */, // S3_3_c15_c15_3 at min EL1: LLC_HASH3 + REG_LLC_WRR =57340 /* 57340 */, // S3_3_c15_c15_4 at min EL1: LLC_WRR + REG_LLC_DRAM_HASH5 =57341 /* 57341 */, // S3_3_c15_c15_5 at min EL1: LLC_DRAM_HASH5 + REG_LLC_DRAM_HASH6 =57342 /* 57342 */, // S3_3_c15_c15_6 at min EL1: LLC_DRAM_HASH6 + REG_VPIDR_EL2 =57344 /* 57344 */, // S3_4_c0_c0_0 at min EL2: VPIDR_EL2 + REG_VMPIDR_EL2 =57349 /* 57349 */, // S3_4_c0_c0_5 at min EL2: VMPIDR_EL2 + REG_SCTLR_EL2 =57472 /* 57472 */, // S3_4_c1_c0_0 at min EL2: SCTLR_EL2 + REG_ACTLR_EL2 =57473 /* 57473 */, // S3_4_c1_c0_1 at min EL2: ACTLR_EL2 + REG_HCR_EL2 =57480 /* 57480 */, // S3_4_c1_c1_0 at min EL2: HCR_EL2 + REG_MDCR_EL2 =57481 /* 57481 */, // S3_4_c1_c1_1 at min EL2: MDCR_EL2 + REG_CPTR_EL2 =57482 /* 57482 */, // S3_4_c1_c1_2 at min EL2: CPTR_EL2 + REG_HSTR_EL2 =57483 /* 57483 */, // S3_4_c1_c1_3 at min EL2: HSTR_EL2 + REG_HFGRTR_EL2 =57484 /* 57484 */, // S3_4_c1_c1_4 at min EL2: HFGRTR_EL2 + REG_HFGWTR_EL2 =57485 /* 57485 */, // S3_4_c1_c1_5 at min EL2: HFGWTR_EL2 + REG_HFGITR_EL2 =57486 /* 57486 */, // S3_4_c1_c1_6 at min EL2: HFGITR_EL2 + REG_HACR_EL2 =57487 /* 57487 */, // S3_4_c1_c1_7 at min EL2: HACR_EL2 + REG_TRFCR_EL2 =57489 /* 57489 */, + REG_HCRX_EL2 =57490 /* 57490 */, // S3_4_c1_c2_2 at min EL2: HCRX_EL2 + REG_SMPRIMAP_EL2 =57493 /* 57493 */, // S3_4_c1_c2_5 at min EL2: SMPRIMAP_EL2 + REG_SMCR_EL2 =57494 /* 57494 */, // S3_4_c1_c2_6 at min EL2: SMCR_EL2 + REG_SDER32_EL2 =57497 /* 57497 */, + REG_TTBR0_EL2 =57600 /* 57600 */, // S3_4_c2_c0_0 at min EL2: TTBR0_EL2 + REG_TTBR1_EL2 =57601 /* 57601 */, // S3_4_c2_c0_1 at min EL2: TTBR1_EL2 + REG_TCR_EL2 =57602 /* 57602 */, // S3_4_c2_c0_2 at min EL2: TCR_EL2 + REG_VTTBR_EL2 =57608 /* 57608 */, // S3_4_c2_c1_0 at min EL2: VTTBR_EL2 + REG_VTCR_EL2 =57610 /* 57610 */, // S3_4_c2_c1_2 at min EL2: VTCR_EL2 + REG_VNCR_EL2 =57616 /* 57616 */, // S3_4_c2_c2_0 at min EL2: VNCR_EL2 + REG_VSTTBR_EL2 =57648 /* 57648 */, + REG_VSTCR_EL2 =57650 /* 57650 */, + REG_DACR32_EL2 =57728 /* 57728 */, // S3_4_c3_c0_0 at min EL2: DACR32_EL2 + REG_HDFGRTR_EL2 =57740 /* 57740 */, // S3_4_c3_c1_4 at min EL2: HDFGRTR_EL2 + REG_HDFGWTR_EL2 =57741 /* 57741 */, // S3_4_c3_c1_5 at min EL2: HDFGWTR_EL2 + REG_SPSR_NV_EL21 =57856 /* 57856 */, // S3_4_c4_c0_0 at min EL1: SPSR_NV_EL21 + REG_SPSR_EL2 =57856 /* 57856 */, + REG_ELR_NV_EL21 =57857 /* 57857 */, // S3_4_c4_c0_1 at min EL1: ELR_NV_EL21 + REG_ELR_EL2 =57857 /* 57857 */, + REG_SP_EL1 =57864 /* 57864 */, // S3_4_c4_c1_0 at min EL1: SP_EL1 + REG_SPSR_IRQ =57880 /* 57880 */, // S3_4_c4_c3_0 at min EL1: SPSR_irq + REG_SPSR_ABT =57881 /* 57881 */, // S3_4_c4_c3_1 at min EL1: SPSR_abt + REG_SPSR_UND =57882 /* 57882 */, // S3_4_c4_c3_2 at min EL1: SPSR_und + REG_SPSR_FIQ =57883 /* 57883 */, // S3_4_c4_c3_3 at min EL1: SPSR_fiq + REG_IFSR32_EL2 =57985 /* 57985 */, // S3_4_c5_c0_1 at min EL2: IFSR32_EL2 + REG_AFSR0_EL2 =57992 /* 57992 */, // S3_4_c5_c1_0 at min EL2: AFSR0_EL2 + REG_AFSR1_EL2 =57993 /* 57993 */, // S3_4_c5_c1_1 at min EL2: AFSR1_EL2 + REG_ESR_NV_EL21 =58000 /* 58000 */, // S3_4_c5_c2_0 at min EL1: ESR_NV_EL21 + REG_ESR_EL2 =58000 /* 58000 */, + REG_VSESR_EL2 =58003 /* 58003 */, // S3_4_c5_c2_3 at min EL2: VSESR_EL2 + REG_FPEXC32_EL2 =58008 /* 58008 */, // S3_4_c5_c3_0 at min EL2: FPEXC32_EL2 + REG_TFSR_EL2 =58032 /* 58032 */, + REG_FAR_NV_EL21 =58112 /* 58112 */, // S3_4_c6_c0_0 at min EL1: FAR_NV_EL21 + REG_FAR_EL2 =58112 /* 58112 */, + REG_HPFAR_EL2 =58116 /* 58116 */, // S3_4_c6_c0_4 at min EL2: HPFAR_EL2 + REG_PMSCR_EL2 =58568 /* 58568 */, + REG_MAIR_EL2 =58640 /* 58640 */, // S3_4_c10_c2_0 at min EL2: MAIR_EL2 + REG_AMAIR_EL2 =58648 /* 58648 */, // S3_4_c10_c3_0 at min EL2: AMAIR_EL2 + REG_MPAMHCR_EL2 =58656 /* 58656 */, + REG_MPAMVPMV_EL2 =58657 /* 58657 */, + REG_MPAM2_EL2 =58664 /* 58664 */, + REG_MPAMVPM0_EL2 =58672 /* 58672 */, + REG_MPAMVPM1_EL2 =58673 /* 58673 */, + REG_MPAMVPM2_EL2 =58674 /* 58674 */, + REG_MPAMVPM3_EL2 =58675 /* 58675 */, + REG_MPAMVPM4_EL2 =58676 /* 58676 */, + REG_MPAMVPM5_EL2 =58677 /* 58677 */, + REG_MPAMVPM6_EL2 =58678 /* 58678 */, + REG_MPAMVPM7_EL2 =58679 /* 58679 */, + REG_VBAR_EL2 =58880 /* 58880 */, // S3_4_c12_c0_0 at min EL2: VBAR_EL2 + REG_RVBAR_EL2 =58881 /* 58881 */, // S3_4_c12_c0_1 at min EL2: RVBAR_EL2 + REG_RMR_EL2 =58882 /* 58882 */, // S3_4_c12_c0_2 at min EL2: RMR_EL2 + REG_VDISR_EL2 =58889 /* 58889 */, // S3_4_c12_c1_1 at min EL2: VDISR_EL2 + REG_ICH_AP0R0_EL2 =58944 /* 58944 */, // S3_4_c12_c8_0 at min EL2: ICH_AP0R0_EL2 + REG_ICH_AP0R1_EL2 =58945 /* 58945 */, + REG_ICH_AP0R2_EL2 =58946 /* 58946 */, + REG_ICH_AP0R3_EL2 =58947 /* 58947 */, + REG_ICH_AP1R0_EL2 =58952 /* 58952 */, // S3_4_c12_c9_0 at min EL2: ICH_AP1R0_EL2 + REG_ICH_AP1R1_EL2 =58953 /* 58953 */, + REG_ICH_AP1R2_EL2 =58954 /* 58954 */, + REG_ICH_AP1R3_EL2 =58955 /* 58955 */, + REG_ICH_VSEIR_EL2 =58956 /* 58956 */, + REG_ICC_SRE_EL2 =58957 /* 58957 */, // S3_4_c12_c9_5 at min EL2: ICC_SRE_EL2 + REG_ICH_HCR_EL2 =58968 /* 58968 */, // S3_4_c12_c11_0 at min EL2: ICH_HCR_EL2 + REG_ICH_VTR_EL2 =58969 /* 58969 */, // S3_4_c12_c11_1 at min EL2: ICH_VTR_EL2 + REG_ICH_MISR_EL2 =58970 /* 58970 */, // S3_4_c12_c11_2 at min EL2: ICH_MISR_EL2 + REG_ICH_EISR_EL2 =58971 /* 58971 */, // S3_4_c12_c11_3 at min EL2: ICH_EISR_EL2 + REG_ICH_ELRSR_EL2 =58973 /* 58973 */, // S3_4_c12_c11_5 at min EL2: ICH_ELRSR_EL2 + REG_ICH_VMCR_EL2 =58975 /* 58975 */, // S3_4_c12_c11_7 at min EL2: ICH_VMCR_EL2 + REG_ICH_LR0_EL2 =58976 /* 58976 */, // S3_4_c12_c12_0 at min EL2: ICH_LR0_EL2 + REG_ICH_LR1_EL2 =58977 /* 58977 */, // S3_4_c12_c12_1 at min EL2: ICH_LR1_EL2 + REG_ICH_LR2_EL2 =58978 /* 58978 */, // S3_4_c12_c12_2 at min EL2: ICH_LR2_EL2 + REG_ICH_LR3_EL2 =58979 /* 58979 */, // S3_4_c12_c12_3 at min EL2: ICH_LR3_EL2 + REG_ICH_LR4_EL2 =58980 /* 58980 */, // S3_4_c12_c12_4 at min EL2: ICH_LR4_EL2 + REG_ICH_LR5_EL2 =58981 /* 58981 */, // S3_4_c12_c12_5 at min EL2: ICH_LR5_EL2 + REG_ICH_LR6_EL2 =58982 /* 58982 */, // S3_4_c12_c12_6 at min EL2: ICH_LR6_EL2 + REG_ICH_LR7_EL2 =58983 /* 58983 */, // S3_4_c12_c12_7 at min EL2: ICH_LR7_EL2 + REG_ICH_LR8_EL2 =58984 /* 58984 */, + REG_ICH_LR9_EL2 =58985 /* 58985 */, + REG_ICH_LR10_EL2 =58986 /* 58986 */, + REG_ICH_LR11_EL2 =58987 /* 58987 */, + REG_ICH_LR12_EL2 =58988 /* 58988 */, + REG_ICH_LR13_EL2 =58989 /* 58989 */, + REG_ICH_LR14_EL2 =58990 /* 58990 */, + REG_ICH_LR15_EL2 =58991 /* 58991 */, + REG_CONTEXTIDR_EL2 =59009 /* 59009 */, // S3_4_c13_c0_1 at min EL2: CONTEXTIDR_EL2 + REG_TPIDR_EL2 =59010 /* 59010 */, // S3_4_c13_c0_2 at min EL2: TPIDR_EL2 + REG_SCXTNUM_EL2 =59015 /* 59015 */, // S3_4_c13_c0_7 at min EL2: SCXTNUM_EL2 + REG_CNTVOFF_EL2 =59139 /* 59139 */, // S3_4_c14_c0_3 at min EL2: CNTVOFF_EL2 + REG_REDIR_CNTHCTL_EL2 =59144 /* 59144 */, // S3_4_c14_c1_0 at min EL2: REDIR_CNTHCTL_EL2 + REG_CNTHCTL_EL2 =59144 /* 59144 */, + REG_REDIR_CNTHP_TVAL_EL2 =59152 /* 59152 */, // S3_4_c14_c2_0 at min EL2: REDIR_CNTHP_TVAL_EL2 + REG_CNTHP_TVAL_EL2 =59152 /* 59152 */, + REG_REDIR_CNTHP_CTL_EL2 =59153 /* 59153 */, // S3_4_c14_c2_1 at min EL2: REDIR_CNTHP_CTL_EL2 + REG_CNTHP_CTL_EL2 =59153 /* 59153 */, + REG_REDIR_CNTHP_CVAL_EL2 =59154 /* 59154 */, // S3_4_c14_c2_2 at min EL2: REDIR_CNTHP_CVAL_EL2 + REG_CNTHP_CVAL_EL2 =59154 /* 59154 */, + REG_REDIR_CNTHV_TVAL_EL2 =59160 /* 59160 */, // S3_4_c14_c3_0 at min EL2: REDIR_CNTHV_TVAL_EL2 + REG_CNTHV_TVAL_EL2 =59160 /* 59160 */, + REG_REDIR_CNTHV_CTL_EL2 =59161 /* 59161 */, // S3_4_c14_c3_1 at min EL2: REDIR_CNTHV_CTL_EL2 + REG_CNTHV_CTL_EL2 =59161 /* 59161 */, + REG_REDIR_CNTHV_CVAL_EL2 =59162 /* 59162 */, // S3_4_c14_c3_2 at min EL2: REDIR_CNTHV_CVAL_EL2 + REG_CNTHV_CVAL_EL2 =59162 /* 59162 */, + REG_CNTHVS_TVAL_EL2 =59168 /* 59168 */, + REG_CNTHVS_CTL_EL2 =59169 /* 59169 */, + REG_CNTHVS_CVAL_EL2 =59170 /* 59170 */, + REG_CNTHPS_TVAL_EL2 =59176 /* 59176 */, + REG_CNTHPS_CTL_EL2 =59177 /* 59177 */, + REG_CNTHPS_CVAL_EL2 =59178 /* 59178 */, + REG_FED_ERR_STS =59264 /* 59264 */, // S3_4_c15_c0_0 at min EL1: FED_ERR_STS + REG_FED_ERR_CTL =59265 /* 59265 */, // S3_4_c15_c0_1 at min EL1: FED_ERR_CTL + REG_APCTL_EL21 =59268 /* 59268 */, // S3_4_c15_c0_4 at min EL1: APCTL_EL21 + REG_KERNKEYLO_EL21 =59272 /* 59272 */, // S3_4_c15_c1_0 at min EL1: KERNKEYLo_EL21 + REG_KERNKEYHI_EL21 =59273 /* 59273 */, // S3_4_c15_c1_1 at min EL1: KERNKEYHi_EL21 + REG_VMSA_LOCK_EL1 =59274 /* 59274 */, // S3_4_c15_c1_2 at min EL1: VMSA_LOCK_EL1 + REG_AMX_STATE_T_EL1 =59275 /* 59275 */, // S3_4_c15_c1_3 at min EL1: AMX_STATE_T_EL1 + REG_AMX_CONFIG_EL21 =59276 /* 59276 */, // S3_4_c15_c1_4 at min EL1: AMX_CONFIG_EL21 + REG_VMSA_LOCK_EL2 =59277 /* 59277 */, // S3_4_c15_c1_5 at min EL2: VMSA_LOCK_EL2 + REG_CTRR_B_UPR_EL21 =59278 /* 59278 */, // S3_4_c15_c1_6 at min EL1: CTRR_B_UPR_EL21 + REG_CTRR_B_LWR_EL21 =59279 /* 59279 */, // S3_4_c15_c1_7 at min EL1: CTRR_B_LWR_EL21 + REG_SP_SETUP_GL21 =59280 /* 59280 */, // S3_4_c15_c2_0 at min EL1: SP_SETUP_GL21 + REG_SP_SETUP_GL2 =59281 /* 59281 */, // S3_4_c15_c2_1 at min EL2: SP_SETUP_GL2 + REG_CTRR_B_CTL_EL21 =59282 /* 59282 */, // S3_4_c15_c2_2 at min EL1: CTRR_B_CTL_EL21 + REG_CTRR_A_LWR_EL21 =59283 /* 59283 */, // S3_4_c15_c2_3 at min EL1: CTRR_A_LWR_EL21 + REG_CTRR_A_UPR_EL21 =59284 /* 59284 */, // S3_4_c15_c2_4 at min EL1: CTRR_A_UPR_EL21 + REG_CTRR_A_CTL_EL21 =59285 /* 59285 */, // S3_4_c15_c2_5 at min EL1: CTRR_A_CTL_EL21 + REG_VMSA_LOCK_EL12 =59286 /* 59286 */, // S3_4_c15_c2_6 at min EL2: VMSA_LOCK_EL12 + REG_AGTCNTV_CTL_EL02 =59287 /* 59287 */, // S3_4_c15_c2_7 at min EL1: AGTCNTV_CTL_EL02 + REG_AMX_STATE_EL1 =59288 /* 59288 */, // S3_4_c15_c3_0 at min EL1: AMX_STATE_EL1 + REG_AMX_STATUS_EL1 =59294 /* 59294 */, // S3_4_c15_c3_6 at min EL1: AMX_STATUS_EL1 + REG_AGTCNTP_CVAL_EL02 =59297 /* 59297 */, // S3_4_c15_c4_1 at min EL1: AGTCNTP_CVAL_EL02 + REG_REDIR_ACNTP_TVAL_EL02 =59298 /* 59298 */, // S3_4_c15_c4_2 at min EL1: REDIR_ACNTP_TVAL_EL02 + REG_AGTCNTP_CTL_EL02 =59299 /* 59299 */, // S3_4_c15_c4_3 at min EL1: AGTCNTP_CTL_EL02 + REG_AGTCNTV_CVAL_EL02 =59300 /* 59300 */, // S3_4_c15_c4_4 at min EL1: AGTCNTV_CVAL_EL02 + REG_AGTCNTV_TVAL_EL02 =59301 /* 59301 */, // S3_4_c15_c4_5 at min EL1: AGTCNTV_TVAL_EL02 + REG_AMX_CONFIG_EL12 =59302 /* 59302 */, // S3_4_c15_c4_6 at min EL2: AMX_CONFIG_EL12 + REG_AMX_CONFIG_EL2 =59303 /* 59303 */, // S3_4_c15_c4_7 at min EL2: AMX_CONFIG_EL2 + REG_SPRR_HUPERM_EL0 =59305 /* 59305 */, // S3_4_c15_c5_1 at min EL1: SPRR_HUPERM_EL0 + REG_SPRR_VUPERM_EL0 =59306 /* 59306 */, // S3_4_c15_c5_2 at min EL1: SPRR_VUPERM_EL0 + REG_CTRR_A_CTL_EL2 =59314 /* 59314 */, // S3_4_c15_c6_2 at min EL2: CTRR_A_CTL_EL2 + REG_CTRR_B_CTL_EL2 =59315 /* 59315 */, // S3_4_c15_c6_3 at min EL2: CTRR_B_CTL_EL2 + REG_CTRR_A_LWR_EL2 =59316 /* 59316 */, // S3_4_c15_c6_4 at min EL2: CTRR_A_LWR_EL2 + REG_CTRR_A_UPR_EL2 =59317 /* 59317 */, // S3_4_c15_c6_5 at min EL2: CTRR_A_UPR_EL2 + REG_CTRR_B_LWR_EL2 =59318 /* 59318 */, // S3_4_c15_c6_6 at min EL2: CTRR_B_LWR_EL2 + REG_CTRR_B_UPR_EL2 =59319 /* 59319 */, // S3_4_c15_c6_7 at min EL2: CTRR_B_UPR_EL2 + REG_SPRR_HUMPRR_EL2 =59320 /* 59320 */, // S3_4_c15_c7_0 at min EL2: SPRR_HUMPRR_EL2 + REG_SPRR_HUPERM_SH01_EL2 =59321 /* 59321 */, // S3_4_c15_c7_1 at min EL2: SPRR_HUPERM_SH01_EL2 + REG_SPRR_HUPERM_SH02_EL2 =59322 /* 59322 */, // S3_4_c15_c7_2 at min EL2: SPRR_HUPERM_SH02_EL2 + REG_SPRR_HUPERM_SH03_EL2 =59323 /* 59323 */, // S3_4_c15_c7_3 at min EL2: SPRR_HUPERM_SH03_EL2 + REG_SPRR_HUPERM_SH04_EL2 =59324 /* 59324 */, // S3_4_c15_c7_4 at min EL2: SPRR_HUPERM_SH04_EL2 + REG_SPRR_HUPERM_SH05_EL2 =59325 /* 59325 */, // S3_4_c15_c7_5 at min EL2: SPRR_HUPERM_SH05_EL2 + REG_SPRR_HUPERM_SH06_EL2 =59326 /* 59326 */, // S3_4_c15_c7_6 at min EL2: SPRR_HUPERM_SH06_EL2 + REG_SPRR_HUPERM_SH07_EL2 =59327 /* 59327 */, // S3_4_c15_c7_7 at min EL2: SPRR_HUPERM_SH07_EL2 + REG_SPRR_VUMPRR_EL1 =59328 /* 59328 */, // S3_4_c15_c8_0 at min EL1: SPRR_VUMPRR_EL1 + REG_SPRR_VUPERM_SH01_EL1 =59329 /* 59329 */, // S3_4_c15_c8_1 at min EL1: SPRR_VUPERM_SH01_EL1 + REG_SPRR_VUPERM_SH02_EL1 =59330 /* 59330 */, // S3_4_c15_c8_2 at min EL1: SPRR_VUPERM_SH02_EL1 + REG_SPRR_VUPERM_SH03_EL1 =59331 /* 59331 */, // S3_4_c15_c8_3 at min EL1: SPRR_VUPERM_SH03_EL1 + REG_SPRR_VUPERM_SH04_EL1 =59332 /* 59332 */, // S3_4_c15_c8_4 at min EL1: SPRR_VUPERM_SH04_EL1 + REG_SPRR_VUPERM_SH05_EL1 =59333 /* 59333 */, // S3_4_c15_c8_5 at min EL1: SPRR_VUPERM_SH05_EL1 + REG_SPRR_VUPERM_SH06_EL1 =59334 /* 59334 */, // S3_4_c15_c8_6 at min EL1: SPRR_VUPERM_SH06_EL1 + REG_SPRR_VUPERM_SH07_EL1 =59335 /* 59335 */, // S3_4_c15_c8_7 at min EL1: SPRR_VUPERM_SH07_EL1 + REG_CTRR_A_LWR_EL12 =59336 /* 59336 */, // S3_4_c15_c9_0 at min EL2: CTRR_A_LWR_EL12 + REG_CTRR_A_UPR_EL12 =59337 /* 59337 */, // S3_4_c15_c9_1 at min EL2: CTRR_A_UPR_EL12 + REG_CTRR_B_LWR_EL12 =59338 /* 59338 */, // S3_4_c15_c9_2 at min EL2: CTRR_B_LWR_EL12 + REG_CTRR_B_UPR_EL12 =59339 /* 59339 */, // S3_4_c15_c9_3 at min EL2: CTRR_B_UPR_EL12 + REG_CTRR_A_CTL_EL12 =59340 /* 59340 */, // S3_4_c15_c9_4 at min EL2: CTRR_A_CTL_EL12 + REG_CTRR_B_CTL_EL12 =59341 /* 59341 */, // S3_4_c15_c9_5 at min EL2: CTRR_B_CTL_EL12 + REG_REDIR_ACNTKCTL_EL1 =59342 /* 59342 */, // S3_4_c15_c9_6 at min EL1: REDIR_ACNTKCTL_EL1 + REG_AGTCNTKCTL_EL12 =59343 /* 59343 */, // S3_4_c15_c9_7 at min EL2: AGTCNTKCTL_EL12 + REG_PREDAKEYLO_EL1 =59344 /* 59344 */, // S3_4_c15_c10_0 at min EL1: PREDAKEYLo_EL1 + REG_PREDAKEYHI_EL1 =59345 /* 59345 */, // S3_4_c15_c10_1 at min EL1: PREDAKEYHi_EL1 + REG_PREDBKEYLO_EL1 =59346 /* 59346 */, // S3_4_c15_c10_2 at min EL1: PREDBKEYLo_EL1 + REG_PREDBKEYHI_EL1 =59347 /* 59347 */, // S3_4_c15_c10_3 at min EL1: PREDBKEYHi_EL1 + REG_SIQ_CFG_EL1 =59348 /* 59348 */, // S3_4_c15_c10_4 at min EL1: SIQ_CFG_EL1 + REG_REDIR_LCL_ACNTPCTSS_EL0 =59349 /* 59349 */, // S3_4_c15_c10_5 at min EL1: REDIR_LCL_ACNTPCTSS_EL0 + REG_REDIR_LCL_ACNTVCTSS_EL0 =59350 /* 59350 */, // S3_4_c15_c10_6 at min EL1: REDIR_LCL_ACNTVCTSS_EL0 + REG_AVNCR_EL2 =59351 /* 59351 */, // S3_4_c15_c10_7 at min EL2: AVNCR_EL2 + REG_ACC_CTRR_A_LWR_EL2 =59352 /* 59352 */, // S3_4_c15_c11_0 at min EL2: ACC_CTRR_A_LWR_EL2 + REG_ACC_CTRR_A_UPR_EL2 =59353 /* 59353 */, // S3_4_c15_c11_1 at min EL2: ACC_CTRR_A_UPR_EL2 + REG_ACC_CTRR_B_LWR_EL2 =59354 /* 59354 */, // S3_4_c15_c11_2 at min EL2: ACC_CTRR_B_LWR_EL2 + REG_ACC_CTRR_B_UPR_EL2 =59355 /* 59355 */, // S3_4_c15_c11_3 at min EL2: ACC_CTRR_B_UPR_EL2 + REG_ACC_CTRR_A_CTL_EL2 =59356 /* 59356 */, // S3_4_c15_c11_4 at min EL2: ACC_CTRR_A_CTL_EL2 + REG_ACC_CTRR_B_CTL_EL2 =59357 /* 59357 */, // S3_4_c15_c11_5 at min EL2: ACC_CTRR_B_CTL_EL2 + REG_REDIR_LCL_ACNTPCT_EL0 =59358 /* 59358 */, // S3_4_c15_c11_6 at min EL1: REDIR_LCL_ACNTPCT_EL0 + REG_REDIR_LCL_ACNTVCT_EL0 =59359 /* 59359 */, // S3_4_c15_c11_7 at min EL1: REDIR_LCL_ACNTVCT_EL0 + REG_ACFG_EL1 =59360 /* 59360 */, // S3_4_c15_c12_0 at min EL1: ACFG_EL1 + REG_AHCR_EL2 =59361 /* 59361 */, // S3_4_c15_c12_1 at min EL2: AHCR_EL2 + REG_APL_INTSTATUS_EL21 =59362 /* 59362 */, // S3_4_c15_c12_2 at min EL1: APL_INTSTATUS_EL21 + REG_APL_INTSTATUS_EL2 =59363 /* 59363 */, // S3_4_c15_c12_3 at min EL2: APL_INTSTATUS_EL2 + REG_REDIR_ACNTHCTL_EL2 =59366 /* 59366 */, // S3_4_c15_c12_6 at min EL2: REDIR_ACNTHCTL_EL2 + REG_JAPIAKEYLO_NV_EL21 =59368 /* 59368 */, // S3_4_c15_c13_0 at min EL1: JAPIAKeyLo_NV_EL21 + REG_JAPIAKEYHI_NV_EL21 =59369 /* 59369 */, // S3_4_c15_c13_1 at min EL1: JAPIAKeyHi_NV_EL21 + REG_JAPIBKEYLO_NV_EL21 =59370 /* 59370 */, // S3_4_c15_c13_2 at min EL1: JAPIBKeyLo_NV_EL21 + REG_JAPIBKEYHI_NV_EL21 =59371 /* 59371 */, // S3_4_c15_c13_3 at min EL1: JAPIBKeyHi_NV_EL21 + REG_JAPIAKEYLO_EL21 =59372 /* 59372 */, // S3_4_c15_c13_4 at min EL1: JAPIAKeyLo_EL21 + REG_JAPIAKEYHI_EL21 =59373 /* 59373 */, // S3_4_c15_c13_5 at min EL1: JAPIAKeyHi_EL21 + REG_JAPIBKEYLO_EL21 =59374 /* 59374 */, // S3_4_c15_c13_6 at min EL1: JAPIBKeyLo_EL21 + REG_JAPIBKEYHI_EL21 =59375 /* 59375 */, // S3_4_c15_c13_7 at min EL1: JAPIBKeyHi_EL21 + REG_JAPIAKEYLO_EL12 =59376 /* 59376 */, // S3_4_c15_c14_0 at min EL2: JAPIAKeyLo_EL12 + REG_JAPIAKEYHI_EL12 =59377 /* 59377 */, // S3_4_c15_c14_1 at min EL2: JAPIAKeyHi_EL12 + REG_JAPIBKEYLO_EL12 =59378 /* 59378 */, // S3_4_c15_c14_2 at min EL2: JAPIBKeyLo_EL12 + REG_JAPIBKEYHI_EL12 =59379 /* 59379 */, // S3_4_c15_c14_3 at min EL2: JAPIBKeyHi_EL12 + REG_AGTCNTRDIR_EL2 =59381 /* 59381 */, // S3_4_c15_c14_5 at min EL2: AGTCNTRDIR_EL2 + REG_AGTCNTRDIR_EL12 =59382 /* 59382 */, // S3_4_c15_c14_6 at min EL2: AGTCNTRDIR_EL12 + REG_JRANGE_EL2 =59384 /* 59384 */, // S3_4_c15_c15_0 at min EL2: JRANGE_EL2 + REG_JRANGE_EL21 =59385 /* 59385 */, // S3_4_c15_c15_1 at min EL1: JRANGE_EL21 + REG_JRANGE_EL12 =59386 /* 59386 */, // S3_4_c15_c15_2 at min EL2: JRANGE_EL12 + REG_JCTL_EL2 =59387 /* 59387 */, // S3_4_c15_c15_3 at min EL2: JCTL_EL2 + REG_JCTL_EL21 =59388 /* 59388 */, // S3_4_c15_c15_4 at min EL1: JCTL_EL21 + REG_JCTL_EL12 =59389 /* 59389 */, // S3_4_c15_c15_5 at min EL2: JCTL_EL12 + REG_JCTL_EL0 =59390 /* 59390 */, // S3_4_c15_c15_6 at min EL1: JCTL_EL0 + REG_AMDSCR_EL1 =59391 /* 59391 */, // S3_4_c15_c15_7 at min EL1: AMDSCR_EL1 + REG_SCTLR_EL12 =59520 /* 59520 */, // S3_5_c1_c0_0 at min EL2: SCTLR_EL12 + REG_ACTLR_EL12 =59521 /* 59521 */, // S3_5_c1_c0_1 at min EL2: ACTLR_EL12 + REG_CPACR_EL12 =59522 /* 59522 */, // S3_5_c1_c0_2 at min EL2: CPACR_EL12 + REG_TRFCR_EL12 =59537 /* 59537 */, + REG_SMCR_EL12 =59542 /* 59542 */, // S3_5_c1_c2_6 at min EL2: SMCR_EL12 + REG_TTBR0_EL12 =59648 /* 59648 */, // S3_5_c2_c0_0 at min EL2: TTBR0_EL12 + REG_TTBR1_EL12 =59649 /* 59649 */, // S3_5_c2_c0_1 at min EL2: TTBR1_EL12 + REG_TCR_EL12 =59650 /* 59650 */, // S3_5_c2_c0_2 at min EL2: TCR_EL12 + REG_SPSR_EL12 =59904 /* 59904 */, // S3_5_c4_c0_0 at min EL2: SPSR_EL12 + REG_ELR_EL12 =59905 /* 59905 */, // S3_5_c4_c0_1 at min EL2: ELR_EL12 + REG_AFSR0_EL12 =60040 /* 60040 */, // S3_5_c5_c1_0 at min EL2: AFSR0_EL12 + REG_AFSR1_EL12 =60041 /* 60041 */, // S3_5_c5_c1_1 at min EL2: AFSR1_EL12 + REG_ESR_EL12 =60048 /* 60048 */, // S3_5_c5_c2_0 at min EL2: ESR_EL12 + REG_TFSR_EL12 =60080 /* 60080 */, + REG_FAR_EL12 =60160 /* 60160 */, // S3_5_c6_c0_0 at min EL2: FAR_EL12 + REG_PMSCR_EL12 =60616 /* 60616 */, + REG_MAIR_EL12 =60688 /* 60688 */, // S3_5_c10_c2_0 at min EL2: MAIR_EL12 + REG_AMAIR_EL12 =60696 /* 60696 */, // S3_5_c10_c3_0 at min EL2: AMAIR_EL12 + REG_MPAM1_EL12 =60712 /* 60712 */, + REG_VBAR_EL12 =60928 /* 60928 */, // S3_5_c12_c0_0 at min EL2: VBAR_EL12 + REG_CONTEXTIDR_EL12 =61057 /* 61057 */, // S3_5_c13_c0_1 at min EL2: CONTEXTIDR_EL12 + REG_SCXTNUM_EL12 =61063 /* 61063 */, // S3_5_c13_c0_7 at min EL2: SCXTNUM_EL12 + REG_CNTKCTL_EL12 =61192 /* 61192 */, // S3_5_c14_c1_0 at min EL2: CNTKCTL_EL12 + REG_CNTP_TVAL_EL02 =61200 /* 61200 */, // S3_5_c14_c2_0 at min EL1: CNTP_TVAL_EL02 + REG_CNTP_CTL_EL02 =61201 /* 61201 */, // S3_5_c14_c2_1 at min EL1: CNTP_CTL_EL02 + REG_CNTP_CVAL_EL02 =61202 /* 61202 */, // S3_5_c14_c2_2 at min EL1: CNTP_CVAL_EL02 + REG_CNTV_TVAL_EL02 =61208 /* 61208 */, // S3_5_c14_c3_0 at min EL1: CNTV_TVAL_EL02 + REG_CNTV_CTL_EL02 =61209 /* 61209 */, // S3_5_c14_c3_1 at min EL1: CNTV_CTL_EL02 + REG_CNTV_CVAL_EL02 =61210 /* 61210 */, // S3_5_c14_c3_2 at min EL1: CNTV_CVAL_EL02 + REG_IPI_RR_LOCAL_EL1 =61312 /* 61312 */, // S3_5_c15_c0_0 at min EL1: IPI_RR_LOCAL_EL1 + REG_IPI_RR_GLOBAL_EL1 =61313 /* 61313 */, // S3_5_c15_c0_1 at min EL1: IPI_RR_GLOBAL_EL1 + REG_AF_ERR_CFG0 =61314 /* 61314 */, // S3_5_c15_c0_2 at min EL1: AF_ERR_CFG0 + REG_AP_ERR_CFG0 =61315 /* 61315 */, // S3_5_c15_c0_3 at min EL1: AP_ERR_CFG0 + REG_AF_ERR_SRC_IDS =61316 /* 61316 */, // S3_5_c15_c0_4 at min EL1: AF_ERR_SRC_IDS + REG_DPC_ERR_STS =61317 /* 61317 */, // S3_5_c15_c0_5 at min EL1: DPC_ERR_STS + REG_DPC_ERR_CTL =61318 /* 61318 */, // S3_5_c15_c0_6 at min EL1: DPC_ERR_CTL + REG_PROD_TRC_CORE_CFG_EL21 =61319 /* 61319 */, // S3_5_c15_c0_7 at min EL1: PROD_TRC_CORE_CFG_EL21 + REG_TRACE_CORE_CFG =61320 /* 61320 */, // S3_5_c15_c1_0 at min EL1: TRACE_CORE_CFG + REG_IPI_SR =61321 /* 61321 */, // S3_5_c15_c1_1 at min EL1: IPI_SR + REG_APL_LRTMR_EL2 =61322 /* 61322 */, // S3_5_c15_c1_2 at min EL2: APL_LRTMR_EL2 + REG_APL_INTENABLE_EL2 =61323 /* 61323 */, // S3_5_c15_c1_3 at min EL2: APL_INTENABLE_EL2 + REG_KTRACE_MESSAGE =61324 /* 61324 */, // S3_5_c15_c1_4 at min EL1: KTRACE_MESSAGE + REG_TRACE_CORE_CFG_EXT =61325 /* 61325 */, // S3_5_c15_c1_5 at min EL1: TRACE_CORE_CFG_EXT + REG_PROD_TRC_CORE_CFG_EL2 =61326 /* 61326 */, // S3_5_c15_c1_6 at min EL2: PROD_TRC_CORE_CFG_EL2 + REG_HID_PROD_TRC_CORE_CFG_EL1 =61327 /* 61327 */, // S3_5_c15_c1_7 at min EL1: HID_PROD_TRC_CORE_CFG_EL1 + REG_DBG_WRAP_GLB =61328 /* 61328 */, // S3_5_c15_c2_0 at min EL1: DBG_WRAP_GLB + REG_TRACE_STREAM_BASE =61329 /* 61329 */, // S3_5_c15_c2_1 at min EL1: TRACE_STREAM_BASE + REG_TRACE_STREAM_FILL =61330 /* 61330 */, // S3_5_c15_c2_2 at min EL1: TRACE_STREAM_FILL + REG_TRACE_STREAM_BASE1 =61331 /* 61331 */, // S3_5_c15_c2_3 at min EL1: TRACE_STREAM_BASE1 + REG_TRACE_STREAM_FILL1 =61332 /* 61332 */, // S3_5_c15_c2_4 at min EL1: TRACE_STREAM_FILL1 + REG_TRACE_STREAM_IRQ =61333 /* 61333 */, // S3_5_c15_c2_5 at min EL1: TRACE_STREAM_IRQ + REG_WATCHDOGDIAG0 =61334 /* 61334 */, // S3_5_c15_c2_6 at min EL1: WatchDogDiag0 + REG_WATCHDOGDIAG1 =61335 /* 61335 */, // S3_5_c15_c2_7 at min EL1: WatchDogDiag1 + REG_TRACE_AUX_CTL =61336 /* 61336 */, // S3_5_c15_c3_0 at min EL1: TRACE_AUX_CTL + REG_IPI_CR =61337 /* 61337 */, // S3_5_c15_c3_1 at min EL1: IPI_CR + REG_UTRIG_EVENT =61338 /* 61338 */, // S3_5_c15_c3_2 at min EL1: UTRIG_EVENT + REG_HID_PROD_TRC_MASK_EL1 =61339 /* 61339 */, // S3_5_c15_c3_3 at min EL1: HID_PROD_TRC_MASK_EL1 + REG_TRACE_CTL =61340 /* 61340 */, // S3_5_c15_c3_4 at min EL1: TRACE_CTL + REG_TRACE_DAT =61341 /* 61341 */, // S3_5_c15_c3_5 at min EL1: TRACE_DAT + REG_PROD_TRC_STRM_BASE0_GL2 =61342 /* 61342 */, // S3_5_c15_c3_6 at min EL2: PROD_TRC_STRM_BASE0_GL2 + REG_PROD_TRC_STRM_BASE1_GL2 =61343 /* 61343 */, // S3_5_c15_c3_7 at min EL2: PROD_TRC_STRM_BASE1_GL2 + REG_CPU_CFG =61344 /* 61344 */, // S3_5_c15_c4_0 at min EL1: CPU_CFG + REG_PBLK_STS =61345 /* 61345 */, // S3_5_c15_c4_1 at min EL1: PBLK_STS + REG_PROD_TRC_CTL_EL21 =61347 /* 61347 */, // S3_5_c15_c4_3 at min EL1: PROD_TRC_CTL_EL21 + REG_PROD_TRC_STRM_BASE0_GL21 =61348 /* 61348 */, // S3_5_c15_c4_4 at min EL1: PROD_TRC_STRM_BASE0_GL21 + REG_PROD_TRC_STRM_BASE1_GL21 =61349 /* 61349 */, // S3_5_c15_c4_5 at min EL1: PROD_TRC_STRM_BASE1_GL21 + REG_PROD_TRC_STRM_FIQ_EL21 =61350 /* 61350 */, // S3_5_c15_c4_6 at min EL1: PROD_TRC_STRM_FIQ_EL21 + REG_CPU_OVRD =61352 /* 61352 */, // S3_5_c15_c5_0 at min EL1: CPU_OVRD + REG_PBLK_EXE_ST =61354 /* 61354 */, // S3_5_c15_c5_2 at min EL1: PBLK_EXE_ST + REG_PROD_TRC_CORE_GL_CTL_GL21 =61357 /* 61357 */, // S3_5_c15_c5_5 at min EL1: PROD_TRC_CORE_GL_CTL_GL21 + REG_PROD_TRC_CORE_GL_CTL_GL2 =61358 /* 61358 */, // S3_5_c15_c5_6 at min EL2: PROD_TRC_CORE_GL_CTL_GL2 + REG_ACC_OVRD =61360 /* 61360 */, // S3_5_c15_c6_0 at min EL1: ACC_OVRD + REG_ACC_OVRD1 =61361 /* 61361 */, // S3_5_c15_c6_1 at min EL1: ACC_OVRD1 + REG_CPM_PWRDN_CTL =61362 /* 61362 */, // S3_5_c15_c6_2 at min EL1: CPM_PWRDN_CTL + REG_PROD_TRC_BUF_RESTORE0_GL21 =61364 /* 61364 */, // S3_5_c15_c6_4 at min EL1: PROD_TRC_BUF_RESTORE0_GL21 + REG_PROD_TRC_BUF_RESTORE1_GL21 =61365 /* 61365 */, // S3_5_c15_c6_5 at min EL1: PROD_TRC_BUF_RESTORE1_GL21 + REG_PROD_TRC_EN_GL21 =61366 /* 61366 */, // S3_5_c15_c6_6 at min EL1: PROD_TRC_EN_GL21 + REG_PRE_LLCFLUSH_TMR =61368 /* 61368 */, // S3_5_c15_c7_0 at min EL1: PRE_LLCFLUSH_TMR + REG_BIUINTFCTL_CFG =61372 /* 61372 */, // S3_5_c15_c7_4 at min EL1: BIUINTFCTL_CFG + REG_BIUINTFWRR_CFG =61373 /* 61373 */, // S3_5_c15_c7_5 at min EL1: BIUINTFWRR_CFG + REG_PRE_TD_TMR =61376 /* 61376 */, // S3_5_c15_c8_0 at min EL1: PRE_TD_TMR + REG_ACC_SLP_WAKE_UP_TMR =61377 /* 61377 */, // S3_5_c15_c8_1 at min EL1: ACC_SLP_WAKE_UP_TMR + REG_PBLK_PSW_DLY =61384 /* 61384 */, // S3_5_c15_c9_0 at min EL1: PBLK_PSW_DLY + REG_CPU_STS =61392 /* 61392 */, // S3_5_c15_c10_0 at min EL1: CPU_STS + REG_HIST_TRIG =61393 /* 61393 */, // S3_5_c15_c10_1 at min EL1: HIST_TRIG + REG_PROD_TRC_BUF_RESTORE0_GL2 =61396 /* 61396 */, // S3_5_c15_c10_4 at min EL2: PROD_TRC_BUF_RESTORE0_GL2 + REG_PROD_TRC_BUF_RESTORE1_GL2 =61397 /* 61397 */, // S3_5_c15_c10_5 at min EL2: PROD_TRC_BUF_RESTORE1_GL2 + REG_PROD_TRC_STRM_FILL0_EL1 =61398 /* 61398 */, // S3_5_c15_c10_6 at min EL1: PROD_TRC_STRM_FILL0_EL1 + REG_PROD_TRC_STRM_FILL1_EL1 =61399 /* 61399 */, // S3_5_c15_c10_7 at min EL1: PROD_TRC_STRM_FILL1_EL1 + REG_ARRAY_INDEX =61400 /* 61400 */, // S3_5_c15_c11_0 at min EL1: ARRAY_INDEX + REG_PROD_TRC_CTL_EL2 =61401 /* 61401 */, // S3_5_c15_c11_1 at min EL2: PROD_TRC_CTL_EL2 + REG_PROD_TRC_EN_GL2 =61402 /* 61402 */, // S3_5_c15_c11_2 at min EL2: PROD_TRC_EN_GL2 + REG_PROD_TRC_STRM_FIQ_EL2 =61403 /* 61403 */, // S3_5_c15_c11_3 at min EL2: PROD_TRC_STRM_FIQ_EL2 + REG_PROD_TRC_CPMU_DUMP_TRIG_EL1=61404 /* 61404 */, // S3_5_c15_c11_4 at min EL1: PROD_TRC_CPMU_DUMP_TRIG_EL1 + REG_PROD_LOSS_COUNT_EL1 =61405 /* 61405 */, // S3_5_c15_c11_5 at min EL1: PROD_LOSS_COUNT_EL1 + REG_SW_TRACE_DATA_EL0 =61406 /* 61406 */, // S3_5_c15_c11_6 at min EL1: SW_TRACE_DATA_EL0 + REG_IL1_DATA0 =61408 /* 61408 */, // S3_5_c15_c12_0 at min EL1: IL1_DATA0 + REG_IL1_DATA1 =61409 /* 61409 */, // S3_5_c15_c12_1 at min EL1: IL1_DATA1 + REG_DL1_DATA0 =61410 /* 61410 */, // S3_5_c15_c12_2 at min EL1: DL1_DATA0 + REG_DL1_DATA1 =61411 /* 61411 */, // S3_5_c15_c12_3 at min EL1: DL1_DATA1 + REG_MMUDATA0 =61412 /* 61412 */, // S3_5_c15_c12_4 at min EL1: MMUDATA0 + REG_MMUDATA1 =61413 /* 61413 */, // S3_5_c15_c12_5 at min EL1: MMUDATA1 + REG_DL1_DATA2 =61414 /* 61414 */, // S3_5_c15_c12_6 at min EL1: DL1_DATA2 + REG_IL1_DATA2 =61415 /* 61415 */, // S3_5_c15_c12_7 at min EL1: IL1_DATA2 + REG_LLC_DATA0 =61420 /* 61420 */, // S3_5_c15_c13_4 at min EL1: LLC_DATA0 + REG_LLC_DATA1 =61421 /* 61421 */, // S3_5_c15_c13_5 at min EL1: LLC_DATA1 + REG_SCTLR_EL3 =61568 /* 61568 */, // S3_6_c1_c0_0 at min EL3: SCTLR_EL3 + REG_ACTLR_EL3 =61569 /* 61569 */, // S3_6_c1_c0_1 at min EL3: ACTLR_EL3 + REG_SCR_EL3 =61576 /* 61576 */, // S3_6_c1_c1_0 at min EL3: SCR_EL3 + REG_SDER32_EL3 =61577 /* 61577 */, // S3_6_c1_c1_1 at min EL3: SDER32_EL3 + REG_CPTR_EL3 =61578 /* 61578 */, // S3_6_c1_c1_2 at min EL3: CPTR_EL3 + REG_MDCR_EL3 =61593 /* 61593 */, // S3_6_c1_c3_1 at min EL3: MDCR_EL3 + REG_TTBR0_EL3 =61696 /* 61696 */, // S3_6_c2_c0_0 at min EL3: TTBR0_EL3 + REG_TCR_EL3 =61698 /* 61698 */, // S3_6_c2_c0_2 at min EL3: TCR_EL3 + REG_SPSR_EL3 =61952 /* 61952 */, // S3_6_c4_c0_0 at min EL3: SPSR_EL3 + REG_ELR_EL3 =61953 /* 61953 */, // S3_6_c4_c0_1 at min EL3: ELR_EL3 + REG_SP_EL2 =61960 /* 61960 */, // S3_6_c4_c1_0 at min EL2: SP_EL2 + REG_AFSR0_EL3 =62088 /* 62088 */, // S3_6_c5_c1_0 at min EL3: AFSR0_EL3 + REG_AFSR1_EL3 =62089 /* 62089 */, // S3_6_c5_c1_1 at min EL3: AFSR1_EL3 + REG_ESR_EL3 =62096 /* 62096 */, // S3_6_c5_c2_0 at min EL3: ESR_EL3 + REG_TFSR_EL3 =62128 /* 62128 */, + REG_FAR_EL3 =62208 /* 62208 */, // S3_6_c6_c0_0 at min EL3: FAR_EL3 + REG_MAIR_EL3 =62736 /* 62736 */, // S3_6_c10_c2_0 at min EL3: MAIR_EL3 + REG_AMAIR_EL3 =62744 /* 62744 */, // S3_6_c10_c3_0 at min EL3: AMAIR_EL3 + REG_MPAM3_EL3 =62760 /* 62760 */, + REG_VBAR_EL3 =62976 /* 62976 */, // S3_6_c12_c0_0 at min EL3: VBAR_EL3 + REG_RVBAR_EL3 =62977 /* 62977 */, // S3_6_c12_c0_1 at min EL3: RVBAR_EL3 + REG_RMR_EL3 =62978 /* 62978 */, // S3_6_c12_c0_2 at min EL3: RMR_EL3 + REG_ICC_CTLR_EL3 =63076 /* 63076 */, + REG_ICC_SRE_EL3 =63077 /* 63077 */, + REG_ICC_IGRPEN1_EL3 =63079 /* 63079 */, + REG_TPIDR_EL3 =63106 /* 63106 */, // S3_6_c13_c0_2 at min EL3: TPIDR_EL3 + REG_SCXTNUM_EL3 =63111 /* 63111 */, + REG_MMU_ERR_STS =63360 /* 63360 */, // S3_6_c15_c0_0 at min EL1: MMU_ERR_STS + REG_AFSR1_GL21 =63361 /* 63361 */, // S3_6_c15_c0_1 at min EL1: AFSR1_GL21 + REG_AFSR1_GL2 =63362 /* 63362 */, // S3_6_c15_c0_2 at min EL2: AFSR1_GL2 + REG_AFSR1_GL12 =63363 /* 63363 */, // S3_6_c15_c0_3 at min EL2: AFSR1_GL12 + REG_BP_OBJC_ADR_EL1 =63364 /* 63364 */, // S3_6_c15_c0_4 at min EL1: BP_OBJC_ADR_EL1 + REG_BP_OBJC_CTL_EL1 =63365 /* 63365 */, // S3_6_c15_c0_5 at min EL1: BP_OBJC_CTL_EL1 + REG_SP_GL11_GL21 =63366 /* 63366 */, // S3_6_c15_c0_6 at min EL1: SP_GL11_GL21 + REG_MMU_SESR_EL2 =63367 /* 63367 */, // S3_6_c15_c0_7 at min EL2: MMU_SESR_EL2 + REG_SPRR_CONFIG_EL21 =63368 /* 63368 */, // S3_6_c15_c1_0 at min EL1: SPRR_CONFIG_EL21 + REG_HPFAR_GL2 =63369 /* 63369 */, // S3_6_c15_c1_1 at min EL2: HPFAR_GL2 + REG_GXF_CONFIG_EL21 =63370 /* 63370 */, // S3_6_c15_c1_2 at min EL1: GXF_CONFIG_EL21 + REG_SPRR_AMRANGE_EL1 =63371 /* 63371 */, // S3_6_c15_c1_3 at min EL1: SPRR_AMRANGE_EL1 + REG_GXF_CONFIG_EL2 =63372 /* 63372 */, // S3_6_c15_c1_4 at min EL2: GXF_CONFIG_EL2 + REG_SPRR_UPERM_EL02 =63373 /* 63373 */, // S3_6_c15_c1_5 at min EL1: SPRR_UPERM_EL02 + REG_SPRR_PPERM_EL21 =63374 /* 63374 */, // S3_6_c15_c1_6 at min EL1: SPRR_PPERM_EL21 + REG_SPRR_PPERM_EL2 =63375 /* 63375 */, // S3_6_c15_c1_7 at min EL2: SPRR_PPERM_EL2 + REG_APGAKEYLO_EL12 =63377 /* 63377 */, // S3_6_c15_c2_1 at min EL2: APGAKeyLo_EL12 + REG_APGAKEYHI_EL12 =63378 /* 63378 */, // S3_6_c15_c2_2 at min EL2: APGAKeyHi_EL12 + REG_KERNKEYLO_EL12 =63379 /* 63379 */, // S3_6_c15_c2_3 at min EL2: KERNKEYLo_EL12 + REG_KERNKEYHI_EL12 =63380 /* 63380 */, // S3_6_c15_c2_4 at min EL2: KERNKEYHi_EL12 + REG_AFPCR_EL0 =63381 /* 63381 */, // S3_6_c15_c2_5 at min EL1: AFPCR_EL0 + REG_SP_GL22 =63382 /* 63382 */, // S3_6_c15_c2_6 at min EL2: SP_GL22 + REG_AMXIDR_EL1 =63383 /* 63383 */, // S3_6_c15_c2_7 at min EL1: AMXIDR_EL1 + REG_SPRR_UMPRR_EL1 =63384 /* 63384 */, // S3_6_c15_c3_0 at min EL1: SPRR_UMPRR_EL1 + REG_SPRR_PMPRR_EL21 =63385 /* 63385 */, // S3_6_c15_c3_1 at min EL1: SPRR_PMPRR_EL21 + REG_SPRR_PMPRR_EL2 =63386 /* 63386 */, // S3_6_c15_c3_2 at min EL2: SPRR_PMPRR_EL2 + REG_SPRR_UPERM_SH01_EL1 =63387 /* 63387 */, // S3_6_c15_c3_3 at min EL1: SPRR_UPERM_SH01_EL1 + REG_SPRR_UPERM_SH02_EL1 =63388 /* 63388 */, // S3_6_c15_c3_4 at min EL1: SPRR_UPERM_SH02_EL1 + REG_SPRR_UPERM_SH03_EL1 =63389 /* 63389 */, // S3_6_c15_c3_5 at min EL1: SPRR_UPERM_SH03_EL1 + REG_SPRR_UPERM_SH04_EL1 =63390 /* 63390 */, // S3_6_c15_c3_6 at min EL1: SPRR_UPERM_SH04_EL1 + REG_SPRR_UPERM_SH05_EL1 =63391 /* 63391 */, // S3_6_c15_c3_7 at min EL1: SPRR_UPERM_SH05_EL1 + REG_SPRR_UPERM_SH06_EL1 =63392 /* 63392 */, // S3_6_c15_c4_0 at min EL1: SPRR_UPERM_SH06_EL1 + REG_SPRR_UPERM_SH07_EL1 =63393 /* 63393 */, // S3_6_c15_c4_1 at min EL1: SPRR_UPERM_SH07_EL1 + REG_SPRR_PPERM_SH01_EL21 =63394 /* 63394 */, // S3_6_c15_c4_2 at min EL1: SPRR_PPERM_SH01_EL21 + REG_SPRR_PPERM_SH02_EL21 =63395 /* 63395 */, // S3_6_c15_c4_3 at min EL1: SPRR_PPERM_SH02_EL21 + REG_SPRR_PPERM_SH03_EL21 =63396 /* 63396 */, // S3_6_c15_c4_4 at min EL1: SPRR_PPERM_SH03_EL21 + REG_SPRR_PPERM_SH04_EL21 =63397 /* 63397 */, // S3_6_c15_c4_5 at min EL1: SPRR_PPERM_SH04_EL21 + REG_SPRR_PPERM_SH05_EL21 =63398 /* 63398 */, // S3_6_c15_c4_6 at min EL1: SPRR_PPERM_SH05_EL21 + REG_SPRR_PPERM_SH06_EL21 =63399 /* 63399 */, // S3_6_c15_c4_7 at min EL1: SPRR_PPERM_SH06_EL21 + REG_SPRR_PPERM_SH07_EL21 =63400 /* 63400 */, // S3_6_c15_c5_0 at min EL1: SPRR_PPERM_SH07_EL21 + REG_SPRR_PPERM_SH01_EL2 =63401 /* 63401 */, // S3_6_c15_c5_1 at min EL2: SPRR_PPERM_SH01_EL2 + REG_SPRR_PPERM_SH02_EL2 =63402 /* 63402 */, // S3_6_c15_c5_2 at min EL2: SPRR_PPERM_SH02_EL2 + REG_SPRR_PPERM_SH03_EL2 =63403 /* 63403 */, // S3_6_c15_c5_3 at min EL2: SPRR_PPERM_SH03_EL2 + REG_SPRR_PPERM_SH04_EL2 =63404 /* 63404 */, // S3_6_c15_c5_4 at min EL2: SPRR_PPERM_SH04_EL2 + REG_SPRR_PPERM_SH05_EL2 =63405 /* 63405 */, // S3_6_c15_c5_5 at min EL2: SPRR_PPERM_SH05_EL2 + REG_SPRR_PPERM_SH06_EL2 =63406 /* 63406 */, // S3_6_c15_c5_6 at min EL2: SPRR_PPERM_SH06_EL2 + REG_SPRR_PPERM_SH07_EL2 =63407 /* 63407 */, // S3_6_c15_c5_7 at min EL2: SPRR_PPERM_SH07_EL2 + REG_SPRR_PMPRR_EL12 =63408 /* 63408 */, // S3_6_c15_c6_0 at min EL2: SPRR_PMPRR_EL12 + REG_SPRR_PPERM_SH01_EL12 =63409 /* 63409 */, // S3_6_c15_c6_1 at min EL2: SPRR_PPERM_SH01_EL12 + REG_SPRR_PPERM_SH02_EL12 =63410 /* 63410 */, // S3_6_c15_c6_2 at min EL2: SPRR_PPERM_SH02_EL12 + REG_SPRR_PPERM_SH03_EL12 =63411 /* 63411 */, // S3_6_c15_c6_3 at min EL2: SPRR_PPERM_SH03_EL12 + REG_SPRR_PPERM_SH04_EL12 =63412 /* 63412 */, // S3_6_c15_c6_4 at min EL2: SPRR_PPERM_SH04_EL12 + REG_SPRR_PPERM_SH05_EL12 =63413 /* 63413 */, // S3_6_c15_c6_5 at min EL2: SPRR_PPERM_SH05_EL12 + REG_SPRR_PPERM_SH06_EL12 =63414 /* 63414 */, // S3_6_c15_c6_6 at min EL2: SPRR_PPERM_SH06_EL12 + REG_SPRR_PPERM_SH07_EL12 =63415 /* 63415 */, // S3_6_c15_c6_7 at min EL2: SPRR_PPERM_SH07_EL12 + REG_APIAKEYLO_EL12 =63416 /* 63416 */, // S3_6_c15_c7_0 at min EL2: APIAKeyLo_EL12 + REG_APIAKEYHI_EL12 =63417 /* 63417 */, // S3_6_c15_c7_1 at min EL2: APIAKeyHi_EL12 + REG_APIBKEYLO_EL12 =63418 /* 63418 */, // S3_6_c15_c7_2 at min EL2: APIBKeyLo_EL12 + REG_APIBKEYHI_EL12 =63419 /* 63419 */, // S3_6_c15_c7_3 at min EL2: APIBKeyHi_EL12 + REG_APDAKEYLO_EL12 =63420 /* 63420 */, // S3_6_c15_c7_4 at min EL2: APDAKeyLo_EL12 + REG_APDAKEYHI_EL12 =63421 /* 63421 */, // S3_6_c15_c7_5 at min EL2: APDAKeyHi_EL12 + REG_APDBKEYLO_EL12 =63422 /* 63422 */, // S3_6_c15_c7_6 at min EL2: APDBKeyLo_EL12 + REG_APDBKEYHI_EL12 =63423 /* 63423 */, // S3_6_c15_c7_7 at min EL2: APDBKeyHi_EL12 + REG_CURRENTG =63424 /* 63424 */, // S3_6_c15_c8_0 at min EL1: CurrentG + REG_GXF_ENTRY_EL21 =63425 /* 63425 */, // S3_6_c15_c8_1 at min EL1: GXF_ENTRY_EL21 + REG_GXF_PABENTRY_EL21 =63426 /* 63426 */, // S3_6_c15_c8_2 at min EL1: GXF_PABENTRY_EL21 + REG_ASPSR_EL21 =63427 /* 63427 */, // S3_6_c15_c8_3 at min EL1: ASPSR_EL21 + REG_ADSPSR_EL0 =63428 /* 63428 */, // S3_6_c15_c8_4 at min EL1: ADSPSR_EL0 + REG_PMCR1_GL2 =63429 /* 63429 */, // S3_6_c15_c8_5 at min EL2: PMCR1_GL2 + REG_ASPSR_NV_EL21 =63430 /* 63430 */, // S3_6_c15_c8_6 at min EL1: ASPSR_NV_EL21 + REG_PMCR1_GL21 =63431 /* 63431 */, // S3_6_c15_c8_7 at min EL1: PMCR1_GL21 + REG_VBAR_GL12 =63434 /* 63434 */, // S3_6_c15_c9_2 at min EL2: VBAR_GL12 + REG_SPSR_GL12 =63435 /* 63435 */, // S3_6_c15_c9_3 at min EL2: SPSR_GL12 + REG_ASPSR_GL12 =63436 /* 63436 */, // S3_6_c15_c9_4 at min EL2: ASPSR_GL12 + REG_ESR_GL12 =63437 /* 63437 */, // S3_6_c15_c9_5 at min EL2: ESR_GL12 + REG_ELR_GL12 =63438 /* 63438 */, // S3_6_c15_c9_6 at min EL2: ELR_GL12 + REG_FAR_GL12 =63439 /* 63439 */, // S3_6_c15_c9_7 at min EL2: FAR_GL12 + REG_SP_GL1 =63440 /* 63440 */, // S3_6_c15_c10_0 at min EL1: SP_GL1 + REG_TPIDR_GL1 =63441 /* 63441 */, // S3_6_c15_c10_1 at min EL1: TPIDR_GL1 + REG_VBAR_GL21 =63442 /* 63442 */, // S3_6_c15_c10_2 at min EL1: VBAR_GL21 + REG_SPSR_GL21 =63443 /* 63443 */, // S3_6_c15_c10_3 at min EL1: SPSR_GL21 + REG_ASPSR_GL21 =63444 /* 63444 */, // S3_6_c15_c10_4 at min EL1: ASPSR_GL21 + REG_ESR_GL21 =63445 /* 63445 */, // S3_6_c15_c10_5 at min EL1: ESR_GL21 + REG_ELR_GL21 =63446 /* 63446 */, // S3_6_c15_c10_6 at min EL1: ELR_GL21 + REG_FAR_GL21 =63447 /* 63447 */, // S3_6_c15_c10_7 at min EL1: FAR_GL21 + REG_SP_GL2 =63448 /* 63448 */, // S3_6_c15_c11_0 at min EL2: SP_GL2 + REG_TPIDR_GL2 =63449 /* 63449 */, // S3_6_c15_c11_1 at min EL2: TPIDR_GL2 + REG_VBAR_GL2 =63450 /* 63450 */, // S3_6_c15_c11_2 at min EL2: VBAR_GL2 + REG_SPSR_GL2 =63451 /* 63451 */, // S3_6_c15_c11_3 at min EL2: SPSR_GL2 + REG_ASPSR_GL2 =63452 /* 63452 */, // S3_6_c15_c11_4 at min EL2: ASPSR_GL2 + REG_ESR_GL2 =63453 /* 63453 */, // S3_6_c15_c11_5 at min EL2: ESR_GL2 + REG_ELR_GL2 =63454 /* 63454 */, // S3_6_c15_c11_6 at min EL2: ELR_GL2 + REG_FAR_GL2 =63455 /* 63455 */, // S3_6_c15_c11_7 at min EL2: FAR_GL2 + REG_GXF_ENTRY_EL2 =63456 /* 63456 */, // S3_6_c15_c12_0 at min EL2: GXF_ENTRY_EL2 + REG_GXF_PABENTRY_EL2 =63457 /* 63457 */, // S3_6_c15_c12_1 at min EL2: GXF_PABENTRY_EL2 + REG_APCTL_EL2 =63458 /* 63458 */, // S3_6_c15_c12_2 at min EL2: APCTL_EL2 + REG_APSTS_EL2 =63459 /* 63459 */, // S3_6_c15_c12_3 at min EL2: APSTS_EL2 + REG_APSTS_NV1_EL1 =63460 /* 63460 */, // S3_6_c15_c12_4 at min EL1: APSTS_NV1_EL1 + REG_KERNKEYLO_NV_EL21 =63461 /* 63461 */, // S3_6_c15_c12_5 at min EL1: KERNKEYLo_NV_EL21 + REG_KERNKEYHI_NV_EL21 =63462 /* 63462 */, // S3_6_c15_c12_6 at min EL1: KERNKEYHi_NV_EL21 + REG_ASPSR_EL12 =63463 /* 63463 */, // S3_6_c15_c12_7 at min EL2: ASPSR_EL12 + REG_APIAKEYLO_NV_EL21 =63464 /* 63464 */, // S3_6_c15_c13_0 at min EL1: APIAKeyLo_NV_EL21 + REG_APIAKEYHI_NV_EL21 =63465 /* 63465 */, // S3_6_c15_c13_1 at min EL1: APIAKeyHi_NV_EL21 + REG_APIBKEYLO_NV_EL21 =63466 /* 63466 */, // S3_6_c15_c13_2 at min EL1: APIBKeyLo_NV_EL21 + REG_APIBKEYHI_NV_EL21 =63467 /* 63467 */, // S3_6_c15_c13_3 at min EL1: APIBKeyHi_NV_EL21 + REG_APDAKEYLO_NV_EL21 =63468 /* 63468 */, // S3_6_c15_c13_4 at min EL1: APDAKeyLo_NV_EL21 + REG_APDAKEYHI_NV_EL21 =63469 /* 63469 */, // S3_6_c15_c13_5 at min EL1: APDAKeyHi_NV_EL21 + REG_APDBKEYLO_NV_EL21 =63470 /* 63470 */, // S3_6_c15_c13_6 at min EL1: APDBKeyLo_NV_EL21 + REG_APDBKEYHI_NV_EL21 =63471 /* 63471 */, // S3_6_c15_c13_7 at min EL1: APDBKeyHi_NV_EL21 + REG_APGAKEYLO_NV_EL21 =63472 /* 63472 */, // S3_6_c15_c14_0 at min EL1: APGAKeyLo_NV_EL21 + REG_APGAKEYHI_NV_EL21 =63473 /* 63473 */, // S3_6_c15_c14_1 at min EL1: APGAKeyHi_NV_EL21 + REG_SPRR_CONFIG_EL2 =63474 /* 63474 */, // S3_6_c15_c14_2 at min EL2: SPRR_CONFIG_EL2 + REG_SPRR_AMRANGE_EL2 =63475 /* 63475 */, // S3_6_c15_c14_3 at min EL2: SPRR_AMRANGE_EL2 + REG_VMKEYLO_EL2 =63476 /* 63476 */, // S3_6_c15_c14_4 at min EL2: VMKEYLo_EL2 + REG_VMKEYHI_EL2 =63477 /* 63477 */, // S3_6_c15_c14_5 at min EL2: VMKEYHi_EL2 + REG_MMU_SFAR_EL2 =63478 /* 63478 */, // S3_6_c15_c14_6 at min EL2: MMU_SFAR_EL2 + REG_APSTS_EL12 =63479 /* 63479 */, // S3_6_c15_c14_7 at min EL2: APSTS_EL12 + REG_APCTL_EL12 =63480 /* 63480 */, // S3_6_c15_c15_0 at min EL2: APCTL_EL12 + REG_GXF_CONFIG_EL12 =63481 /* 63481 */, // S3_6_c15_c15_1 at min EL2: GXF_CONFIG_EL12 + REG_GXF_ENTRY_EL12 =63482 /* 63482 */, // S3_6_c15_c15_2 at min EL2: GXF_ENTRY_EL12 + REG_GXF_PABENTRY_EL12 =63483 /* 63483 */, // S3_6_c15_c15_3 at min EL2: GXF_PABENTRY_EL12 + REG_SPRR_CONFIG_EL12 =63484 /* 63484 */, // S3_6_c15_c15_4 at min EL2: SPRR_CONFIG_EL12 + REG_SPRR_AMRANGE_EL12 =63485 /* 63485 */, // S3_6_c15_c15_5 at min EL2: SPRR_AMRANGE_EL12 + REG_MMU_SESR_CTL_EL2 =63486 /* 63486 */, // S3_6_c15_c15_6 at min EL2: MMU_SESR_CTL_EL2 + REG_SPRR_PPERM_EL12 =63487 /* 63487 */, // S3_6_c15_c15_7 at min EL2: SPRR_PPERM_EL12 + REG_CNTPS_TVAL_EL1 =65296 /* 65296 */, // S3_7_c14_c2_0 at min EL1: CNTPS_TVAL_EL1 + REG_CNTPS_CTL_EL1 =65297 /* 65297 */, // S3_7_c14_c2_1 at min EL1: CNTPS_CTL_EL1 + REG_CNTPS_CVAL_EL1 =65298 /* 65298 */, // S3_7_c14_c2_2 at min EL1: CNTPS_CVAL_EL1 + REG_PSTATE_SPSEL =65299 /* 65299 */, // (op0,op1,crn,crm,op2)=(0,0,4,9,5) doesn't map to [SYSREG_NONE+1, SYSREG_END) + REG_PWRDNSAVE0 =65408 /* 65408 */, // S3_7_c15_c0_0 at min EL1: PWRDNSAVE0 + REG_NRG_ACC_CTL =65409 /* 65409 */, // S3_7_c15_c0_1 at min EL1: NRG_ACC_CTL + REG_AON_CNT0 =65410 /* 65410 */, // S3_7_c15_c0_2 at min EL1: AON_CNT0 + REG_CPU_CNT0 =65411 /* 65411 */, // S3_7_c15_c0_3 at min EL1: CPU_CNT0 + REG_UPMCR0_EL1 =65412 /* 65412 */, // S3_7_c15_c0_4 at min EL1: UPMCR0_EL1 + REG_UPMC8 =65413 /* 65413 */, // S3_7_c15_c0_5 at min EL1: UPMC8 + REG_AON_CNT8 =65414 /* 65414 */, // S3_7_c15_c0_6 at min EL1: AON_CNT8 + REG_PWRDNSAVE1 =65416 /* 65416 */, // S3_7_c15_c1_0 at min EL1: PWRDNSAVE1 + REG_CORE_NRG_ACC_DAT =65417 /* 65417 */, // S3_7_c15_c1_1 at min EL1: CORE_NRG_ACC_DAT + REG_AON_CNT_CTL0 =65418 /* 65418 */, // S3_7_c15_c1_2 at min EL1: AON_CNT_CTL0 + REG_CPU_CNT_CTL0 =65419 /* 65419 */, // S3_7_c15_c1_3 at min EL1: CPU_CNT_CTL0 + REG_UPMESR0_EL1 =65420 /* 65420 */, // S3_7_c15_c1_4 at min EL1: UPMESR0_EL1 + REG_UPMC9 =65421 /* 65421 */, // S3_7_c15_c1_5 at min EL1: UPMC9 + REG_AON_CNT_CTL8 =65422 /* 65422 */, // S3_7_c15_c1_6 at min EL1: AON_CNT_CTL8 + REG_ACC_PWR_DN_SAVE =65424 /* 65424 */, // S3_7_c15_c2_0 at min EL1: ACC_PWR_DN_SAVE + REG_CPM_NRG_ACC_DAT =65425 /* 65425 */, // S3_7_c15_c2_1 at min EL1: CPM_NRG_ACC_DAT + REG_AON_CNT1 =65426 /* 65426 */, // S3_7_c15_c2_2 at min EL1: AON_CNT1 + REG_CPU_CNT1 =65427 /* 65427 */, // S3_7_c15_c2_3 at min EL1: CPU_CNT1 + REG_UPMSWCTRL_EL1 =65428 /* 65428 */, // S3_7_c15_c2_4 at min EL1: UPMSWCTRL_EL1 + REG_UPMC10 =65429 /* 65429 */, // S3_7_c15_c2_5 at min EL1: UPMC10 + REG_AON_CNT9 =65430 /* 65430 */, // S3_7_c15_c2_6 at min EL1: AON_CNT9 + REG_CORE_SRM_NRG_ACC_DAT =65433 /* 65433 */, // S3_7_c15_c3_1 at min EL1: CORE_SRM_NRG_ACC_DAT + REG_AON_CNT_CTL1 =65434 /* 65434 */, // S3_7_c15_c3_2 at min EL1: AON_CNT_CTL1 + REG_CPU_CNT_CTL1 =65435 /* 65435 */, // S3_7_c15_c3_3 at min EL1: CPU_CNT_CTL1 + REG_UPMECM0_EL1 =65436 /* 65436 */, // S3_7_c15_c3_4 at min EL1: UPMECM0_EL1 + REG_UPMC11 =65437 /* 65437 */, // S3_7_c15_c3_5 at min EL1: UPMC11 + REG_AON_CNT_CTL9 =65438 /* 65438 */, // S3_7_c15_c3_6 at min EL1: AON_CNT_CTL9 + REG_AON_CNT_CTL =65440 /* 65440 */, // S3_7_c15_c4_0 at min EL1: AON_CNT_CTL + REG_CPM_SRM_NRG_ACC_DAT =65441 /* 65441 */, // S3_7_c15_c4_1 at min EL1: CPM_SRM_NRG_ACC_DAT + REG_AON_CNT2 =65442 /* 65442 */, // S3_7_c15_c4_2 at min EL1: AON_CNT2 + REG_CPU_CNT2 =65443 /* 65443 */, // S3_7_c15_c4_3 at min EL1: CPU_CNT2 + REG_UPMECM1_EL1 =65444 /* 65444 */, // S3_7_c15_c4_4 at min EL1: UPMECM1_EL1 + REG_UPMC12 =65445 /* 65445 */, // S3_7_c15_c4_5 at min EL1: UPMC12 + REG_AON_CNT10 =65446 /* 65446 */, // S3_7_c15_c4_6 at min EL1: AON_CNT10 + REG_CPU_CNT_CTL =65448 /* 65448 */, // S3_7_c15_c5_0 at min EL1: CPU_CNT_CTL + REG_AON_CNT_CTL2 =65450 /* 65450 */, // S3_7_c15_c5_2 at min EL1: AON_CNT_CTL2 + REG_CPU_CNT_CTL2 =65451 /* 65451 */, // S3_7_c15_c5_3 at min EL1: CPU_CNT_CTL2 + REG_UPMPCM_EL1 =65452 /* 65452 */, // S3_7_c15_c5_4 at min EL1: UPMPCM_EL1 + REG_UPMC13 =65453 /* 65453 */, // S3_7_c15_c5_5 at min EL1: UPMC13 + REG_AON_CNT_CTL10 =65454 /* 65454 */, // S3_7_c15_c5_6 at min EL1: AON_CNT_CTL10 + REG_AON_CNT3 =65458 /* 65458 */, // S3_7_c15_c6_2 at min EL1: AON_CNT3 + REG_CPU_CNT3 =65459 /* 65459 */, // S3_7_c15_c6_3 at min EL1: CPU_CNT3 + REG_UPMSR_EL1 =65460 /* 65460 */, // S3_7_c15_c6_4 at min EL1: UPMSR_EL1 + REG_UPMC14 =65461 /* 65461 */, // S3_7_c15_c6_5 at min EL1: UPMC14 + REG_AON_CNT11 =65462 /* 65462 */, // S3_7_c15_c6_6 at min EL1: AON_CNT11 + REG_AON_CNT_CTL3 =65466 /* 65466 */, // S3_7_c15_c7_2 at min EL1: AON_CNT_CTL3 + REG_CPU_CNT_CTL3 =65467 /* 65467 */, // S3_7_c15_c7_3 at min EL1: CPU_CNT_CTL3 + REG_UPMC0 =65468 /* 65468 */, // S3_7_c15_c7_4 at min EL1: UPMC0 + REG_UPMC15 =65469 /* 65469 */, // S3_7_c15_c7_5 at min EL1: UPMC15 + REG_AON_CNT_CTL11 =65470 /* 65470 */, // S3_7_c15_c7_6 at min EL1: AON_CNT_CTL11 + REG_AON_CNT4 =65474 /* 65474 */, // S3_7_c15_c8_2 at min EL1: AON_CNT4 + REG_CPU_CNT4 =65475 /* 65475 */, // S3_7_c15_c8_3 at min EL1: CPU_CNT4 + REG_UPMC1 =65476 /* 65476 */, // S3_7_c15_c8_4 at min EL1: UPMC1 + REG_UPMECM2_EL1 =65477 /* 65477 */, // S3_7_c15_c8_5 at min EL1: UPMECM2_EL1 + REG_AON_CNT_CTL4 =65482 /* 65482 */, // S3_7_c15_c9_2 at min EL1: AON_CNT_CTL4 + REG_CPU_CNT_CTL4 =65483 /* 65483 */, // S3_7_c15_c9_3 at min EL1: CPU_CNT_CTL4 + REG_UPMC2 =65484 /* 65484 */, // S3_7_c15_c9_4 at min EL1: UPMC2 + REG_UPMECM3_EL1 =65485 /* 65485 */, // S3_7_c15_c9_5 at min EL1: UPMECM3_EL1 + REG_AON_CNT5 =65490 /* 65490 */, // S3_7_c15_c10_2 at min EL1: AON_CNT5 + REG_CPU_CNT5 =65491 /* 65491 */, // S3_7_c15_c10_3 at min EL1: CPU_CNT5 + REG_UPMC3 =65492 /* 65492 */, // S3_7_c15_c10_4 at min EL1: UPMC3 + REG_UPMCR1_EL1 =65493 /* 65493 */, // S3_7_c15_c10_5 at min EL1: UPMCR1_EL1 + REG_AON_CNT_CTL5 =65498 /* 65498 */, // S3_7_c15_c11_2 at min EL1: AON_CNT_CTL5 + REG_CPU_CNT_CTL5 =65499 /* 65499 */, // S3_7_c15_c11_3 at min EL1: CPU_CNT_CTL5 + REG_UPMC4 =65500 /* 65500 */, // S3_7_c15_c11_4 at min EL1: UPMC4 + REG_UPMESR1_EL1 =65501 /* 65501 */, // S3_7_c15_c11_5 at min EL1: UPMESR1_EL1 + REG_AON_CNT6 =65506 /* 65506 */, // S3_7_c15_c12_2 at min EL1: AON_CNT6 + REG_CPU_CNT6 =65507 /* 65507 */, // S3_7_c15_c12_3 at min EL1: CPU_CNT6 + REG_UPMC5 =65508 /* 65508 */, // S3_7_c15_c12_4 at min EL1: UPMC5 + REG_AON_CNT_CTL6 =65514 /* 65514 */, // S3_7_c15_c13_2 at min EL1: AON_CNT_CTL6 + REG_CPU_CNT_CTL6 =65515 /* 65515 */, // S3_7_c15_c13_3 at min EL1: CPU_CNT_CTL6 + REG_UPMC6 =65516 /* 65516 */, // S3_7_c15_c13_4 at min EL1: UPMC6 + REG_AON_CNT7 =65522 /* 65522 */, // S3_7_c15_c14_2 at min EL1: AON_CNT7 + REG_CPU_CNT7 =65523 /* 65523 */, // S3_7_c15_c14_3 at min EL1: CPU_CNT7 + REG_UPMC7 =65524 /* 65524 */, // S3_7_c15_c14_4 at min EL1: UPMC7 + REG_AON_CNT_CTL7 =65530 /* 65530 */, // S3_7_c15_c15_2 at min EL1: AON_CNT_CTL7 + REG_CPU_CNT_CTL7 =65531 /* 65531 */, // S3_7_c15_c15_3 at min EL1: CPU_CNT_CTL7 + SYSREG_END=65532 +}; +#ifdef __cplusplus +extern "C" { +#endif +bool has_system_register_name(enum SystemReg); +#ifdef __cplusplus +} +#endif |