diff options
| author | Galen Williamson <galen@vector35.com> | 2024-06-13 20:26:33 -0400 |
|---|---|---|
| committer | Galen Williamson <galen@vector35.com> | 2024-06-13 20:26:36 -0400 |
| commit | f4eb81635006d8bbfe1a4a7550d62ae3163117a3 (patch) | |
| tree | c1d8aa96b20033eaa64da502d963852129bd9421 /arch/arm64/il.cpp | |
| parent | e01e3b66e1d7e7fb28750e946f3b9e8fd740284b (diff) | |
[arm64]: fix broken compilation on windows
no Elvis operator ?:(
api\arch\arm64\il.cpp(894): error C2059: syntax error: ':'
api\arch\arm64\il.cpp(1839): error C7555: use of designated initializers requires at least '/std:c++20'
Diffstat (limited to 'arch/arm64/il.cpp')
| -rw-r--r-- | arch/arm64/il.cpp | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/arch/arm64/il.cpp b/arch/arm64/il.cpp index e7ff35e8..12865568 100644 --- a/arch/arm64/il.cpp +++ b/arch/arm64/il.cpp @@ -891,7 +891,7 @@ static void LoadStoreOperandSize(LowLevelILFunction& il, bool load, bool sign_ex if (load) { // LLIL_TEMP registers will be reported to have size 0, so override with size - size_t extendSize = REGSZ_O(operand1) ?: size; + size_t extendSize = REGSZ_O(operand1) ? REGSZ_O(operand1) : size; switch (operand2.operandClass) { case MEM_REG: @@ -1836,7 +1836,11 @@ bool GetLowLevelILForInstruction( case ARM64_LDADDAL: { // TODO: represent/annotate (model?) acquire/release memory ordering semantics for all LDADD* instructions - InstructionOperand tmp = { .reg = { (Register) LLIL_TEMP(0) } }; + + // I want to do this, but I also don't want to add an #ifdef __clang__ + // InstructionOperand tmp = { .reg = { (Register) LLIL_TEMP(0) } }; + InstructionOperand tmp; + tmp.reg[0] = (Register) LLIL_TEMP(0); LoadStoreOperandSize(il, true, false, REGSZ_O(operand2), tmp, operand3); il.AddInstruction(il.Store(REGSZ_O(operand2), ILREG_O(operand3), il.Add(REGSZ_O(operand1), @@ -1860,7 +1864,9 @@ bool GetLowLevelILForInstruction( case ARM64_LDADDLB: case ARM64_LDADDALB: { - InstructionOperand tmp = { .reg = { (Register) LLIL_TEMP(0) } }; + // InstructionOperand tmp = { .reg = { (Register) LLIL_TEMP(0) } }; + InstructionOperand tmp; + tmp.reg[0] = (Register) LLIL_TEMP(0); LoadStoreOperandSize(il, true, false, 1, tmp, operand3); il.AddInstruction(il.Store(1, ILREG_O(operand3), il.Add(1, il.LowPart(1, ILREG_O(operand1)), il.LowPart(1, il.Register(1, LLIL_TEMP(0)))))); @@ -1881,7 +1887,9 @@ bool GetLowLevelILForInstruction( case ARM64_LDADDLH: case ARM64_LDADDALH: { - InstructionOperand tmp = { .reg = { (Register) LLIL_TEMP(0) } }; + // InstructionOperand tmp = { .reg = { (Register) LLIL_TEMP(0) } }; + InstructionOperand tmp; + tmp.reg[0] = (Register) LLIL_TEMP(0); LoadStoreOperandSize(il, true, false, 2, tmp, operand3); il.AddInstruction(il.Store(2, ILREG_O(operand3), il.Add(2, il.LowPart(2, ILREG_O(operand1)), il.LowPart(2, il.Register(2, LLIL_TEMP(0)))))); |