diff options
| author | Galen Williamson <galen@vector35.com> | 2024-07-08 14:32:41 -0400 |
|---|---|---|
| committer | Galen Williamson <galen@vector35.com> | 2024-07-08 14:52:35 -0400 |
| commit | c3040ecfc43983af6f05da13cf2242d085b1e230 (patch) | |
| tree | 79303619d58f7ac45ddb5c5abdd4a8b70ced65a8 /arch/arm64/il.h | |
| parent | 362015687dd159d5235242dfbb13dedfa43f9fef (diff) | |
[arm64] Full review of intrinsics; lifting of many instructions added, improved, and/or fixed
Merged https://github.com/Vector35/binaryninja-api/pull/5461:
Author: yrp <yrp604@protonmail.com>
Date: Sat May 25 21:00:26 2024 -0700
arm64: lift sxtl, sxtl2, sshll, sshll2
Partial list of detailed changes squashed into this commit (see
https://github.com/Vector35/binaryninja-api/tree/arm64_improving_intrinsics
for detailed commit history):
* add lifting for sshll/sxtl
* reverted neon_intrinsics.cpp to restore scvtf intrinsics
* lifted sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and changed the lifting of uxtl/2 to be consistent with sxtl/2
* reformatted arm64test.py and added tests for sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and uxtl/2
fix scvtf (unroll because no intrinsic) and fsub (missing register assignment) half-precision vector cases
* added preferIntrinsics setting to arm64
* added lifting for movn
* fixed incorrect int/float conversions for FMOV, made half-precision immediates survive the lift to M/HLIL
* fix missing break in SCVT; optimize MOVK
* improved preferIntrinsics
* fixed bad lifting introduced for movn
* fixed bad settings definition for preferIntrinsics
* added intrinsic definition for DUP from general register
* added direct lifting of scalar version of FADDP, and fixed intrinsics for vector version
* added direct lifting of scalar version of FABD, and fixed intrinsics for vector version
* fixes to test_gen.py: gets the correct encoding instead of sometimes getting fooled by the mnemonic
* fixed lifting of UCVTF; reviewed/fixed all intrinsics through SQXTUN
* reviewed/fixed remaining intrinsics after SQXTUN
* added lifting for FNMUL
* WIP intrinsics improvements
* WIP intrinsics improvements 2
* WIP intrinsics improvements: FCVT*_asisdmisc_R
* added B.AL, B.NV, CASP*
* direct lifting of scalar FSQRT instruction
* SETREG now elides setting of targeting zero registers
* fixed test_gen.py to correctly regenerate arm64test.py
* unroll vector MOV operations, USHL no longer uses intrinsic for scalars
* updated existing tests in arm64test.py for latest lifting changes
* fixed CASH* and CASB* incorrectly accessing temp register in comparison (resulting in comparing to NOP)
* lifting all variants of TBL as intrinsic
* fixes/improvements to test_gen.py
* lifting all variants of TBX as intrinsic
* added tests for CAS*, UMUL*, UADD*, FABD, FABS, FADDP, FMAX, FMAXNM, FMIN, FMINNM, FNEG, FNMUL, FCMEQ, FCMGE, FCMGT, FMLA, FMLS
* added tests for all aliases of SBFM
Diffstat (limited to 'arch/arm64/il.h')
| -rw-r--r-- | arch/arm64/il.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/il.h b/arch/arm64/il.h index 4ce5904c..e345e395 100644 --- a/arch/arm64/il.h +++ b/arch/arm64/il.h @@ -101,7 +101,7 @@ enum Arm64FakeRegister : uint32_t }; bool GetLowLevelILForInstruction(BinaryNinja::Architecture* arch, uint64_t addr, - BinaryNinja::LowLevelILFunction& il, Instruction& instr, size_t addrSize, bool alignmentRequired); + BinaryNinja::LowLevelILFunction& il, Instruction& instr, size_t addrSize, bool alignmentRequired, std::function<bool()> preferIntrinsics); BinaryNinja::ExprId ExtractRegister(BinaryNinja::LowLevelILFunction& il, InstructionOperand& operand, size_t regNum, size_t extractSize, bool signExtend, |