diff options
| author | Galen Williamson <galen@vector35.com> | 2024-07-08 14:32:41 -0400 |
|---|---|---|
| committer | Galen Williamson <galen@vector35.com> | 2024-07-08 14:52:35 -0400 |
| commit | c3040ecfc43983af6f05da13cf2242d085b1e230 (patch) | |
| tree | 79303619d58f7ac45ddb5c5abdd4a8b70ced65a8 /arch/arm64/misc | |
| parent | 362015687dd159d5235242dfbb13dedfa43f9fef (diff) | |
[arm64] Full review of intrinsics; lifting of many instructions added, improved, and/or fixed
Merged https://github.com/Vector35/binaryninja-api/pull/5461:
Author: yrp <yrp604@protonmail.com>
Date: Sat May 25 21:00:26 2024 -0700
arm64: lift sxtl, sxtl2, sshll, sshll2
Partial list of detailed changes squashed into this commit (see
https://github.com/Vector35/binaryninja-api/tree/arm64_improving_intrinsics
for detailed commit history):
* add lifting for sshll/sxtl
* reverted neon_intrinsics.cpp to restore scvtf intrinsics
* lifted sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and changed the lifting of uxtl/2 to be consistent with sxtl/2
* reformatted arm64test.py and added tests for sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and uxtl/2
fix scvtf (unroll because no intrinsic) and fsub (missing register assignment) half-precision vector cases
* added preferIntrinsics setting to arm64
* added lifting for movn
* fixed incorrect int/float conversions for FMOV, made half-precision immediates survive the lift to M/HLIL
* fix missing break in SCVT; optimize MOVK
* improved preferIntrinsics
* fixed bad lifting introduced for movn
* fixed bad settings definition for preferIntrinsics
* added intrinsic definition for DUP from general register
* added direct lifting of scalar version of FADDP, and fixed intrinsics for vector version
* added direct lifting of scalar version of FABD, and fixed intrinsics for vector version
* fixes to test_gen.py: gets the correct encoding instead of sometimes getting fooled by the mnemonic
* fixed lifting of UCVTF; reviewed/fixed all intrinsics through SQXTUN
* reviewed/fixed remaining intrinsics after SQXTUN
* added lifting for FNMUL
* WIP intrinsics improvements
* WIP intrinsics improvements 2
* WIP intrinsics improvements: FCVT*_asisdmisc_R
* added B.AL, B.NV, CASP*
* direct lifting of scalar FSQRT instruction
* SETREG now elides setting of targeting zero registers
* fixed test_gen.py to correctly regenerate arm64test.py
* unroll vector MOV operations, USHL no longer uses intrinsic for scalars
* updated existing tests in arm64test.py for latest lifting changes
* fixed CASH* and CASB* incorrectly accessing temp register in comparison (resulting in comparing to NOP)
* lifting all variants of TBL as intrinsic
* fixes/improvements to test_gen.py
* lifting all variants of TBX as intrinsic
* added tests for CAS*, UMUL*, UADD*, FABD, FABS, FADDP, FMAX, FMAXNM, FMIN, FMINNM, FNEG, FNMUL, FCMEQ, FCMGE, FCMGT, FMLA, FMLS
* added tests for all aliases of SBFM
Diffstat (limited to 'arch/arm64/misc')
| -rw-r--r-- | arch/arm64/misc/neon_intrins.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/misc/neon_intrins.c b/arch/arm64/misc/neon_intrins.c index 181ee74e..ff0e5efc 100644 --- a/arch/arm64/misc/neon_intrins.c +++ b/arch/arm64/misc/neon_intrins.c @@ -1245,10 +1245,13 @@ float32x2_t vcvt_f32_s32(int32x2_t a); // SCVT float32x4_t vcvtq_f32_s32(int32x4_t a); // SCVTF Vd.4S,Vn.4S float32x2_t vcvt_f32_u32(uint32x2_t a); // UCVTF Vd.2S,Vn.2S float32x4_t vcvtq_f32_u32(uint32x4_t a); // UCVTF Vd.4S,Vn.4S +float32_t vcvts_f32_s32(int32_t a); // SCVTF Sd,Sn float32_t vcvts_f32_u32(uint32_t a); // UCVTF Sd,Sn +float64x1_t vcvt_f64_s64(int64x1_t a); // SCVTF Dd,Dn float64x2_t vcvtq_f64_s64(int64x2_t a); // SCVTF Vd.2D,Vn.2D float64x1_t vcvt_f64_u64(uint64x1_t a); // UCVTF Dd,Dn float64x2_t vcvtq_f64_u64(uint64x2_t a); // UCVTF Vd.2D,Vn.2D +float64_t vcvtd_f64_s64(int64_t a); // SCVTF Dd,Dn float64_t vcvtd_f64_u64(uint64_t a); // UCVTF Dd,Dn float32x2_t vcvt_n_f32_s32(int32x2_t a, const int n); // SCVTF Vd.2S,Vn.2S,#n float32x4_t vcvtq_n_f32_s32(int32x4_t a, const int n); // SCVTF Vd.4S,Vn.4S,#n @@ -4281,6 +4284,9 @@ uint16_t vcgezh_f16(float16_t a); // FCMGE Hd uint16_t vcgtzh_f16(float16_t a); // FCMGT Hd,Hn,#0 uint16_t vclezh_f16(float16_t a); // FCMLE Hd,Hn,#0 uint16_t vcltzh_f16(float16_t a); // FCMLT Hd,Hn,#0 +float16_t vcvth_f16_s16(int16_t a); // SCVTF Hd,Hn +float16_t vcvth_f16_s32(int32_t a); // SCVTF Hd,Hn +float16_t vcvth_f16_s64(int64_t a); // SCVTF Hd,Hn float16_t vcvth_f16_u16(uint16_t a); // UCVTF Hd,Hn float16_t vcvth_f16_u32(uint32_t a); // UCVTF Hd,Hn float16_t vcvth_f16_u64(uint64_t a); // UCVTF Hd,Hn |