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| author | Galen Williamson <galen@vector35.com> | 2024-05-30 17:30:03 -0400 |
|---|---|---|
| committer | Galen Williamson <galen@vector35.com> | 2024-05-30 18:53:40 -0400 |
| commit | 12d47835b1127605d224178e8e67c29f609a1a86 (patch) | |
| tree | ccf82466faa7ea38b50eb8241ffa9a2893de36f4 /arch/arm64/neon_intrinsics.cpp | |
| parent | b3f88b7741b04975126c074609f1fa24475e64ba (diff) | |
[arm64] lift scvtf
* only scalar variants for integer and floating point
* updated arm64test.py for scvtf
* removed intrinsics for scvtf, scalar integer and floating point variants
Diffstat (limited to 'arch/arm64/neon_intrinsics.cpp')
| -rw-r--r-- | arch/arm64/neon_intrinsics.cpp | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/arch/arm64/neon_intrinsics.cpp b/arch/arm64/neon_intrinsics.cpp index 037fc1ae..c8058137 100644 --- a/arch/arm64/neon_intrinsics.cpp +++ b/arch/arm64/neon_intrinsics.cpp @@ -17594,22 +17594,6 @@ bool NeonGetLowLevelILForInstruction( add_input_reg(inputs, il, instr.operands[2]); add_output_reg(outputs, il, instr.operands[0]); break; - case ENC_SCVTF_D64_FLOAT2INT: - // Lift instruction such as `scvtf d3, x15` to vcvtd_f64_s64(int64_t) - intrin_id = ARM64_INTRIN_VCVTD_F64_S64; // SCVTF Dd,Dn - add_input_reg(inputs, il, instr.operands[1]); - add_output_reg(outputs, il, instr.operands[0]); - break; - case ENC_SCVTF_D32_FLOAT2INT: - intrin_id = ARM64_INTRIN_VCVT_F64_S64; // SCVTF Dd,Dn - add_input_reg(inputs, il, instr.operands[1]); - add_output_reg(outputs, il, instr.operands[0]); - break; - case ENC_SCVTF_S32_FLOAT2INT: - intrin_id = ARM64_INTRIN_VCVTS_F32_S32; // SCVTF Sd,Sn - add_input_reg(inputs, il, instr.operands[1]); - add_output_reg(outputs, il, instr.operands[0]); - break; case ENC_SCVTF_ASIMDMISCFP16_R: if (instr.operands[1].arrSpec == ARRSPEC_2SINGLES) intrin_id = ARM64_INTRIN_VCVT_F32_S32; // SCVTF Vd.2S,Vn.2S @@ -17634,11 +17618,6 @@ bool NeonGetLowLevelILForInstruction( add_input_reg(inputs, il, instr.operands[1]); add_output_reg(outputs, il, instr.operands[0]); break; - case ENC_SCVTF_ASISDMISCFP16_R: - intrin_id = ARM64_INTRIN_VCVTH_F16_S16; // SCVTF Hd,Hn - add_input_reg(inputs, il, instr.operands[1]); - add_output_reg(outputs, il, instr.operands[0]); - break; case ENC_SDOT_ASIMDELEM_D: if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES) intrin_id = ARM64_INTRIN_VDOT_LANE_S32; // SDOT Vd.2S,Vn.8B,Vm.4B[lane] |