diff options
| author | Mark Rowe <mark@vector35.com> | 2025-09-18 11:46:39 -0700 |
|---|---|---|
| committer | Mark Rowe <mark@vector35.com> | 2025-09-25 08:41:48 -0700 |
| commit | 6e1306923c60b3d6c1cefb1fcc240f1a064d6f20 (patch) | |
| tree | 57fb65f74fecfa95dd394ecc5b664512d8f87609 /arch/arm64/neon_intrinsics.cpp | |
| parent | 0deeb4a61749737b98f7946ec88b693068180e28 (diff) | |
[AArch64] Update disassembler based on 2025-06 ARM ISA data
Alongside this I also added support for decoding:
* LDR / STR (table)
* PMULLB / PMULLT
* ABS / CNT / CTZ
* SMIN / SMAX / UMIN / UMAX
* RPRFM
* PSEL
Note that while these instructions will now be disassembled, they are
not yet lifted to LLIL.
Additionally, I fixed a number of errors in the decoding of some less
commonly occurring instructions.
Diffstat (limited to 'arch/arm64/neon_intrinsics.cpp')
| -rw-r--r-- | arch/arm64/neon_intrinsics.cpp | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/arch/arm64/neon_intrinsics.cpp b/arch/arm64/neon_intrinsics.cpp index 02e13047..8be1d649 100644 --- a/arch/arm64/neon_intrinsics.cpp +++ b/arch/arm64/neon_intrinsics.cpp @@ -16686,7 +16686,7 @@ bool NeonGetLowLevelILForInstruction( add_input_reg(inputs, il, instr.operands[2]); add_output_reg(outputs, il, instr.operands[0]); break; - case ENC_FCMLA_ASIMDELEM_C_H: + case ENC_FCMLA_ADVSIMD_ELT: if (instr.operands[0].arrSpec == ARRSPEC_4HALVES && instr.operands[1].arrSpec == ARRSPEC_4HALVES && instr.operands[2].arrSpec == ARRSPEC_1HALF && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 0)) // float16x4_t vcmla_laneq_f16(float16x4_t r, float16x4_t a, float16x8_t b, const int lane) // argprep: r -> Vd.4H; a -> Vn.4H; b -> Vm.H; lane -> <lane> @@ -16727,15 +16727,7 @@ bool NeonGetLowLevelILForInstruction( // argprep: r -> Vd.8H; a -> Vn.8H; b -> Vm.H; lane -> <lane> // results: Vd.8H -> result intrin_id = ARM64_INTRIN_VCMLAQ_ROT90_LANEQ_F16; // FCMLA Vd.8H,Vn.8H,Vm.H[lane],#90 - add_input_reg(inputs, il, instr.operands[0]); - add_input_reg(inputs, il, instr.operands[1]); - add_input_reg(inputs, il, instr.operands[2]); - add_input_lane(inputs, il, instr.operands[2]); - add_input_imm(inputs, il, instr.operands[3]); - add_output_reg(outputs, il, instr.operands[0]); - break; - case ENC_FCMLA_ASIMDELEM_C_S: - if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 0)) + else if (instr.operands[0].arrSpec == ARRSPEC_2SINGLES && instr.operands[1].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].arrSpec == ARRSPEC_2SINGLES && instr.operands[2].laneUsed && (instr.operands[3].operandClass && instr.operands[3].operandClass <= FIMM32 && instr.operands[3].immediate == 0)) // float32x2_t vcmla_lane_f32(float32x2_t r, float32x2_t a, float32x2_t b, const int lane) // argprep: r -> Vd.2S; a -> Vn.2S; b -> Vm.2S; lane -> <lane> // results: Vd.2S -> result |