[arm64] Full review of intrinsics; lifting of many instructions added, improved, and/or fixed

Merged https://github.com/Vector35/binaryninja-api/pull/5461:
    Author: yrp <yrp604@protonmail.com>
    Date:   Sat May 25 21:00:26 2024 -0700

        arm64: lift sxtl, sxtl2, sshll, sshll2

Partial list of detailed changes squashed into this commit (see
https://github.com/Vector35/binaryninja-api/tree/arm64_improving_intrinsics
for detailed commit history):

* add lifting for sshll/sxtl

* reverted neon_intrinsics.cpp to restore scvtf intrinsics

* lifted sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and changed the lifting of uxtl/2 to be consistent with sxtl/2

* reformatted arm64test.py and added tests for sxtl/2, sshll, ushll, sshl, sshr, ushl, ushr, and uxtl/2

 fix scvtf (unroll because no intrinsic) and fsub (missing register assignment) half-precision vector cases

* added preferIntrinsics setting to arm64

* added lifting for movn

* fixed incorrect int/float conversions for FMOV, made half-precision immediates survive the lift to M/HLIL

* fix missing break in SCVT; optimize MOVK

* improved preferIntrinsics

* fixed bad lifting introduced for movn

* fixed bad settings definition for preferIntrinsics

* added intrinsic definition for DUP from general register

* added direct lifting of scalar version of FADDP, and fixed intrinsics for vector version

* added direct lifting of scalar version of FABD, and fixed intrinsics for vector version

* fixes to test_gen.py: gets the correct encoding instead of sometimes getting fooled by the mnemonic

* fixed lifting of UCVTF; reviewed/fixed all intrinsics through SQXTUN

* reviewed/fixed remaining intrinsics after SQXTUN

* added lifting for FNMUL

* WIP intrinsics improvements

* WIP intrinsics improvements 2

* WIP intrinsics improvements: FCVT*_asisdmisc_R

* added B.AL, B.NV, CASP*

* direct lifting of scalar FSQRT instruction

* SETREG now elides setting of targeting zero registers

* fixed test_gen.py to correctly regenerate arm64test.py

* unroll vector MOV operations, USHL no longer uses intrinsic for scalars

* updated existing tests in arm64test.py for latest lifting changes

* fixed CASH* and CASB* incorrectly accessing temp register in comparison (resulting in comparing to NOP)

* lifting all variants of TBL as intrinsic

* fixes/improvements to test_gen.py

* lifting all variants of TBX as intrinsic

* added tests for CAS*, UMUL*, UADD*, FABD, FABS, FADDP, FMAX, FMAXNM, FMIN, FMINNM, FNEG, FNMUL, FCMEQ, FCMGE, FCMGT, FMLA, FMLS

* added tests for all aliases of SBFM

1 files changed, 57 insertions, 0 deletions

diff --git a/arch/arm64/neon_intrinsics.h b/arch/arm64/neon_intrinsics.h
index e2dd9616..087b8664 100644
--- a/arch/arm64/neon_intrinsics.h
+++ b/arch/arm64/neon_intrinsics.h
@@ -3926,6 +3926,63 @@ enum NeonIntrinsic : uint32_t
 	ARM64_INTRIN_VBFMLALBQ_LANEQ_F32,
 	ARM64_INTRIN_VBFMLALTQ_LANE_F32,
 	ARM64_INTRIN_VBFMLALTQ_LANEQ_F32,
+	// Added to resolve collisions between vector and scalar variants of the intrinsic
+	ARM64_INTRIN_VMAX__F32,
+	ARM64_INTRIN_VMAXNM__F32,
+	// Added to fill in obvious gaps
+	ARM64_INTRIN_VCVTNS_S64_F32,
+	ARM64_INTRIN_VCVTN_S32_F64,
+	ARM64_INTRIN_VCVTD_N_F64_S32,
+	ARM64_INTRIN_VCVTS_N_F32_S64,
+	ARM64_INTRIN_VCVT_S32_F64,
+	ARM64_INTRIN_VCVT_U32_F64,
+	ARM64_INTRIN_VCVTA_S32_F64,
+	ARM64_INTRIN_VCVTA_U32_F64,
+	ARM64_INTRIN_VCVTAD_S32_F64,
+	ARM64_INTRIN_VCVTAD_U32_F64,
+	ARM64_INTRIN_VCVTAS_N_S32_F32,
+	ARM64_INTRIN_VCVTAS_N_U32_F32,
+	ARM64_INTRIN_VCVTD_S32_F64,
+	ARM64_INTRIN_VCVTD_U32_F64,
+	ARM64_INTRIN_VCVTM_S32_F64,
+	ARM64_INTRIN_VCVTM_U32_F64,
+	ARM64_INTRIN_VCVTMD_S32_F64,
+	ARM64_INTRIN_VCVTMD_U32_F64,
+	ARM64_INTRIN_VCVTMS_N_S32_F32,
+	ARM64_INTRIN_VCVTMS_N_U32_F32,
+	ARM64_INTRIN_VCVTN_U32_F64,
+	ARM64_INTRIN_VCVTND_S32_F64,
+	ARM64_INTRIN_VCVTND_U32_F64,
+	ARM64_INTRIN_VCVTP_S32_F64,
+	ARM64_INTRIN_VCVTP_U32_F64,
+	ARM64_INTRIN_VCVTPD_S32_F64,
+	ARM64_INTRIN_VCVTPD_U32_F64,
+	ARM64_INTRIN_VCVTPS_N_S32_F32,
+	ARM64_INTRIN_VCVTPS_N_U32_F32,
+	ARM64_INTRIN_VCVTA_N_S64_F64,
+	ARM64_INTRIN_VCVTA_N_U64_F64,
+	ARM64_INTRIN_VCVTAD_N_S64_F64,
+	ARM64_INTRIN_VCVTAD_N_U64_F64,
+	ARM64_INTRIN_VCVTM_N_S64_F64,
+	ARM64_INTRIN_VCVTM_N_U64_F64,
+	ARM64_INTRIN_VCVTMD_N_S64_F64,
+	ARM64_INTRIN_VCVTMD_N_U64_F64,
+	ARM64_INTRIN_VCVTP_N_S64_F64,
+	ARM64_INTRIN_VCVTP_N_U64_F64,
+	ARM64_INTRIN_VCVTPD_N_S64_F64,
+	ARM64_INTRIN_VCVTPD_N_U64_F64,
+	ARM64_INTRIN_VCVTNS_U64_F32,
+	ARM64_INTRIN_VCVTPS_U64_F32,
+	ARM64_INTRIN_VCVTPS_S64_F32,
+	ARM64_INTRIN_VCVTS_S64_F32,
+	ARM64_INTRIN_VCVTS_U64_F32,
+	ARM64_INTRIN_VCVTD_N_U64_F32,
+	ARM64_INTRIN_VCVTD_N_U32_F64,
+	ARM64_INTRIN_VCVTS_N_U64_F32,
+	ARM64_INTRIN_VCVTS_N_U32_F64,
+	ARM64_INTRIN_VCVTS_N_U64_F64,
+	ARM64_INTRIN_VCVT_U64_F32,
+	// The end, add more above
 	ARM64_INTRIN_NEON_END
 };