diff options
| author | Galen Williamson <galen@vector35.com> | 2025-06-09 19:30:13 -0400 |
|---|---|---|
| committer | Galen Williamson <galen@vector35.com> | 2025-06-09 19:30:13 -0400 |
| commit | 35c2a4cf35589e1c3046ecbe2c480a57b6d10360 (patch) | |
| tree | 9c95fc3d75c0c376c82e4fbe7e197ec5352260f8 /arch/armv7/arch_armv7.cpp | |
| parent | 9373cab26ee2e7b2febab7674360d54d6fb8adc6 (diff) | |
[thumb2] Converted MSR system registers into enum
Diffstat (limited to 'arch/armv7/arch_armv7.cpp')
| -rw-r--r-- | arch/armv7/arch_armv7.cpp | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/arch/armv7/arch_armv7.cpp b/arch/armv7/arch_armv7.cpp index 08191de5..5739a8bd 100644 --- a/arch/armv7/arch_armv7.cpp +++ b/arch/armv7/arch_armv7.cpp @@ -1895,19 +1895,21 @@ vector<uint32_t> ArmCommonArchitecture::GetAllRegisters() REG_Q8, REG_Q9, REG_Q10, REG_Q11, REG_Q12, REG_Q13, REG_Q14, REG_Q15, /* special registers */ - REGS_APSR, REGS_APSR_G, REGS_APSR_NZCVQ, REGS_APSR_NZCVQG, - REGS_CPSR, REGS_CPSR_C, REGS_CPSR_X, REGS_CPSR_XC, - REGS_CPSR_S, REGS_CPSR_SC, REGS_CPSR_SX, REGS_CPSR_SXC, - REGS_CPSR_F, REGS_CPSR_FC, REGS_CPSR_FX, REGS_CPSR_FXC, - REGS_CPSR_FS, REGS_CPSR_FSC, REGS_CPSR_FSX, REGS_CPSR_FSXC, - REGS_SPSR, REGS_SPSR_C, REGS_SPSR_X, REGS_SPSR_XC, - REGS_SPSR_S, REGS_SPSR_SC, REGS_SPSR_SX, REGS_SPSR_SXC, - REGS_SPSR_F, REGS_SPSR_FC, REGS_SPSR_FX, REGS_SPSR_FXC, - REGS_SPSR_FS, REGS_SPSR_FSC, REGS_SPSR_FSX, REGS_SPSR_FSXC, - REGS_APSR_NZCV, REGS_FPSID, REGS_FPSCR, REGS_MVFR2, + // REGS_APSR, REGS_APSR_G, REGS_APSR_NZCVQ, REGS_APSR_NZCVQG, + // REGS_CPSR, REGS_CPSR_C, REGS_CPSR_X, REGS_CPSR_XC, + // REGS_CPSR_S, REGS_CPSR_SC, REGS_CPSR_SX, REGS_CPSR_SXC, + // REGS_CPSR_F, REGS_CPSR_FC, REGS_CPSR_FX, REGS_CPSR_FXC, + // REGS_CPSR_FS, REGS_CPSR_FSC, REGS_CPSR_FSX, REGS_CPSR_FSXC, + // REGS_SPSR, REGS_SPSR_C, REGS_SPSR_X, REGS_SPSR_XC, + // REGS_SPSR_S, REGS_SPSR_SC, REGS_SPSR_SX, REGS_SPSR_SXC, + // REGS_SPSR_F, REGS_SPSR_FC, REGS_SPSR_FX, REGS_SPSR_FXC, + // REGS_SPSR_FS, REGS_SPSR_FSC, REGS_SPSR_FSX, REGS_SPSR_FSXC, + // REGS_APSR_NZCV, + REGS_FPSID, REGS_FPSCR, REGS_MVFR2, REGS_MVFR1, REGS_MVFR0, REGS_FPEXC, REGS_FPINST, - REGS_FPINST2, REGS_MSP, REGS_PSP, REGS_PRIMASK, - REGS_BASEPRI, REGS_FAULTMASK, REGS_CONTROL, + REGS_FPINST2, + // REGS_MSP, REGS_PSP, REGS_PRIMASK, + // REGS_BASEPRI, REGS_FAULTMASK, REGS_CONTROL, /* fake registers */ FAKEREG_SYSCALL_INFO |