diff options
| author | Galen Williamson <galen@vector35.com> | 2025-07-23 13:56:24 -0400 |
|---|---|---|
| committer | Galen Williamson <galen@vector35.com> | 2025-08-14 14:06:49 -0400 |
| commit | d6e13c753b30260b182cfe433e4e275244a4ab78 (patch) | |
| tree | e5872f325dc26012646d999af94d937942ada0f8 /arch/armv7/il.cpp | |
| parent | ce38990dae2d88d96793715d40544c7e5ece524d (diff) | |
[armv7/thumb2] Fix Lifting for PC-relative vldr instruction does not align PC when calculating address #6947
Updated thumb2 pcode parser used by disassembler generator to use Tatsu instead of deprecated Grako
Diffstat (limited to 'arch/armv7/il.cpp')
| -rw-r--r-- | arch/armv7/il.cpp | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/armv7/il.cpp b/arch/armv7/il.cpp index 7e5d4d90..de53689b 100644 --- a/arch/armv7/il.cpp +++ b/arch/armv7/il.cpp @@ -4933,6 +4933,30 @@ bool GetLowLevelILForArmInstruction(Architecture* arch, uint64_t addr, LowLevelI ConditionExecute(il, instr.cond, SetRegisterOrBranch(il, op1.reg, il.DivUnsigned(get_register_size(op2.reg), ReadRegisterOrPointer(il, op2, addr), ReadRegisterOrPointer(il, op3, addr)))); break; + case ARMV7_VCVT: + switch (instr.dataType) + { + case DT_S32: + case DT_U32: + switch (instr.dataType2) + { + case DT_F32: + case DT_F64: + // ConditionExecute(il, instr.cond, + // il.SetRegister(get_register_size(op1.reg), op1.reg, + // il.FloatToInt(4, il.Register(get_register_size(op2.reg), op2.reg)))); + ConditionExecute(il, instr.cond, + il.SetRegister(get_register_size(op1.reg), op1.reg, + il.FloatToInt(get_register_size(op1.reg), il.Register(get_register_size(op2.reg), op2.reg)))); + break; + default: + break; + } + break; + default: + break; + } + break; case ARMV7_VADD: if((instr.dataType != DT_F32) && (instr.dataType != DT_F64)) break; |