diff options
| author | Mason Reed <mason@vector35.com> | 2024-08-22 12:47:59 -0400 |
|---|---|---|
| committer | mason <35282038+emesare@users.noreply.github.com> | 2024-08-27 11:16:59 -0700 |
| commit | ea781c5e40a7fcf295d42bc406bc76e3640caa7d (patch) | |
| tree | 30e515b16c896bd99c5dc803995315bbe32a374c /arch/armv7 | |
| parent | 7de3cd73aa3790ba642dbcd9bf178ad8482b4ae7 (diff) | |
Lift VMOV
Diffstat (limited to 'arch/armv7')
| -rw-r--r-- | arch/armv7/thumb2_disasm/il_thumb2.cpp | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/armv7/thumb2_disasm/il_thumb2.cpp b/arch/armv7/thumb2_disasm/il_thumb2.cpp index 5d8c6c57..522a492e 100644 --- a/arch/armv7/thumb2_disasm/il_thumb2.cpp +++ b/arch/armv7/thumb2_disasm/il_thumb2.cpp @@ -1476,6 +1476,45 @@ bool GetLowLevelILForNEONInstruction(Architecture* arch, LowLevelILFunction& il, case armv7::ARMV7_VSUB: il.AddInstruction(WriteArithOperand(il, instr, il.Sub(GetRegisterSize(instr, 0), ReadILOperand(il, instr, 1), ReadILOperand(il, instr, 2)))); break; + case armv7::ARMV7_VMOV: + if (instr->format->operandCount == 4) + { + // s1 <- r2, s2 <- r4 + // r1 <- s0, r7 <- s1 + il.AddInstruction(WriteILOperand(il, instr, 0, ReadILOperand(il, instr, 2))); + il.AddInstruction(WriteILOperand(il, instr, 1, ReadILOperand(il, instr, 3))); + } + if (instr->format->operandCount == 3) + { + if (instr->format->operands[2].type == OPERAND_FORMAT_REG_FP) + { + // r3:r2 <- d12 + // The set reg will constrain the 8 byte to 4 byte _probably_. + il.AddInstruction(WriteILOperand(il, instr, 0, ReadILOperand(il, instr, 2))); + il.AddInstruction(WriteILOperand(il, instr, 1, il.LogicalShiftRight(4, ReadILOperand(il, instr, 2), il.Const(1, 32)))); + } else + { + // d9 <- r1:r0 + il.AddInstruction(WriteILOperand(il, instr, 0, il.Or(4, + il.ShiftLeft(4, ReadILOperand(il, instr, 2), il.Const(1, 32)), + ReadILOperand(il, instr, 1)))); + } + } + else + { + if (instr->format->operands[1].type == OPERAND_FORMAT_IMM64 && strcmp(instr->format->operands[0].prefix, "q") == 0) + { + // Load immediate in high and low + il.AddInstruction(WriteILOperand(il, instr, 0, + il.Or(16, ReadILOperand(il, instr, 1), + il.ShiftLeft(16, ReadILOperand(il, instr, 1), + il.Const(8, 64))))); + } + // r2 <= s4 + // s12 <- r8 + il.AddInstruction(WriteILOperand(il, instr, 0, ReadILOperand(il, instr, 1))); + } + break; case armv7::ARMV7_VPUSH: { // TODO: Clean this code up... |