diff options
| author | noone <you@example.com> | 2024-07-31 20:47:28 -0500 |
|---|---|---|
| committer | Alexander Taylor <alex@vector35.com> | 2024-08-12 15:50:54 -0400 |
| commit | bdc1c7134e14fc18182e33dfa3fe98ba10c38acf (patch) | |
| tree | 51394bf04591f1b3335997b3595365cc75cdeeca /arch/mips/il.cpp | |
| parent | 0bf72f94c49f34fc550c2d5c2fbab7a95ac72628 (diff) | |
Add IL, intrinsics for TLB-related instructions
Diffstat (limited to 'arch/mips/il.cpp')
| -rw-r--r-- | arch/mips/il.cpp | 35 |
1 files changed, 31 insertions, 4 deletions
diff --git a/arch/mips/il.cpp b/arch/mips/il.cpp index 14639e74..9719c4f5 100644 --- a/arch/mips/il.cpp +++ b/arch/mips/il.cpp @@ -1842,6 +1842,37 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu il.AddInstruction(il.Intrinsic({}, MIPS_INTRIN_CACHE, {il.Const(1, op1.immediate), GetILOperandMemoryAddress(il, op2, addrSize)})); break; + case MIPS_TLBP: + il.AddInstruction(il.Intrinsic({RegisterOrFlag::Register(REG_INDEX)}, MIPS_INTRIN_TLBSEARCH, {il.Register(registerSize, REG_ENTRY_HI)})); + break; + case MIPS_TLBR: + il.AddInstruction(il.Intrinsic({ + RegisterOrFlag::Register(REG_PAGE_MASK), + RegisterOrFlag::Register(REG_ENTRY_HI), + RegisterOrFlag::Register(REG_ENTRY_LO1), + RegisterOrFlag::Register(REG_ENTRY_LO0) + }, MIPS_INTRIN_TLBGET, { il.Register(registerSize, REG_INDEX) })); + break; + case MIPS_TLBWI: + il.AddInstruction(il.Intrinsic({}, MIPS_INTRIN_TLBSET, { + il.Register(registerSize, REG_INDEX), + il.Register(registerSize, REG_PAGE_MASK), + il.Register(registerSize, REG_ENTRY_HI), + il.Register(registerSize, REG_ENTRY_LO1), + il.Register(registerSize, REG_ENTRY_LO0) + })); + break; + case MIPS_TLBWR: + il.AddInstruction(il.Intrinsic({}, MIPS_INTRIN_TLBSET, { + il.Register(registerSize, REG_RANDOM), + il.Register(registerSize, REG_PAGE_MASK), + il.Register(registerSize, REG_ENTRY_HI), + il.Register(registerSize, REG_ENTRY_LO1), + il.Register(registerSize, REG_ENTRY_LO0) + })); + break; + + case CNMIPS_BADDU: il.AddInstruction(SetRegisterOrNop(il, 8, registerSize, op1.reg, il.ZeroExtend(registerSize, @@ -2135,10 +2166,6 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu case MIPS_MTHC1: case MIPS_MTHC2: case MIPS_PREFX: - case MIPS_TLBP: - case MIPS_TLBR: - case MIPS_TLBWI: - case MIPS_TLBWR: case MIPS_WRPGPR: case MIPS_RDPGPR: case MIPS_RECIP1: |