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| author | noone <you@example.com> | 2024-07-31 19:53:51 -0500 |
|---|---|---|
| committer | Alexander Taylor <alex@vector35.com> | 2024-08-12 15:50:54 -0400 |
| commit | 0bf72f94c49f34fc550c2d5c2fbab7a95ac72628 (patch) | |
| tree | dd5dc1d0298b208bd4d03149e82edba05fc4d8b4 /arch/mips/il.h | |
| parent | c79af77b50dee80dcba9800e42e94eb6abb3e53a (diff) | |
Add intrinsics for some system instructions
Except for SYNCI, I didn't have any test cases for these, but they're
fairly simple.
Diffstat (limited to 'arch/mips/il.h')
| -rw-r--r-- | arch/mips/il.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/il.h b/arch/mips/il.h index abb3d939..c4ffff75 100644 --- a/arch/mips/il.h +++ b/arch/mips/il.h @@ -22,9 +22,11 @@ enum MipsIntrinsic : uint32_t MIPS_INTRIN_DMTC2, MIPS_INTRIN_DMTC_UNIMPLEMENTED, MIPS_INTRIN_SYNC, + MIPS_INTRIN_SYNCI, MIPS_INTRIN_DI, MIPS_INTRIN_EHB, MIPS_INTRIN_EI, + MIPS_INTRIN_PAUSE, MIPS_INTRIN_WAIT, MIPS_INTRIN_HWR0, MIPS_INTRIN_HWR1, @@ -36,6 +38,7 @@ enum MipsIntrinsic : uint32_t MIPS_INTRIN_LLBIT_CHECK, MIPS_INTRIN_PREFETCH, MIPS_INTRIN_CACHE, + MIPS_INTRIN_SDBBP, // there's no clean way to lift LWL/LWR, SWL/SWR, etc when not // a pair of adjacent instructions, since the number and position |