diff options
| author | kat <kat@vector35.com> | 2025-01-12 16:54:50 -0500 |
|---|---|---|
| committer | Galen Williamson <galen@vector35.com> | 2025-07-02 02:11:30 -0400 |
| commit | da9df164ea310ee6aab900fa940b63d20839c2dc (patch) | |
| tree | 590a3bfc40c2e17ba7337c3bd5ff1d16cdf113f7 /arch/mips/il.h | |
| parent | 8303adc8095926ad8e4f3758f5e2677fa20450ce (diff) | |
[mips] Merges PR https://github.com/Vector35/binaryninja-api/pull/6311: MIPS r5900 (PS2 EE) support
Diffstat (limited to 'arch/mips/il.h')
| -rw-r--r-- | arch/mips/il.h | 86 |
1 files changed, 84 insertions, 2 deletions
diff --git a/arch/mips/il.h b/arch/mips/il.h index df84f4a6..2c7d0413 100644 --- a/arch/mips/il.h +++ b/arch/mips/il.h @@ -79,6 +79,15 @@ enum MipsIntrinsic : uint32_t CNMIPS_INTRIN_HWR31, CNMIPS_INTRIN_POP, CNMIPS_INTRIN_DPOP, + + MIPS_INTRIN_R5900_VWAITQ, + MIPS_INTRIN_R5900_VU_MEM_LOAD, + MIPS_INTRIN_R5900_VU_MEM_STORE, + MIPS_INTRIN_R5900_VU0_CALLMS, + MIPS_INTRIN_R5900_VU0_CALLMSR, + + MIPS_INTRIN_COP0_CONDITION, + MIPS_INTRIN_INVALID=0xFFFFFFFF, }; @@ -88,6 +97,79 @@ bool GetLowLevelILForInstruction( BinaryNinja::LowLevelILFunction& il, mips::Instruction& instr, size_t addrSize, - uint32_t decomposeFlags); + uint32_t decomposeFlags, + mips::MipsVersion version); + +BinaryNinja::ExprId GetConditionForInstruction(BinaryNinja::LowLevelILFunction& il, mips::Instruction& instr, std::function<size_t(mips::InstructionOperand&)> registerSize); +#ifdef __cplusplus +extern "C" { + namespace mips { +#endif -BinaryNinja::ExprId GetConditionForInstruction(BinaryNinja::LowLevelILFunction& il, mips::Instruction& instr, size_t registerSize); +static inline const size_t get_register_width(size_t reg, MipsVersion version, size_t maxWidth=8) { + size_t width = 32; + switch (version) + { + case MIPS_1: + width = 32; + break; + case MIPS_2: + case MIPS_3: + case MIPS_4: + case MIPS_32: + if (reg < FPREG_F0 || reg > FPREG_F31) + { + width = 32; + break; + } + case MIPS_64: + width = 64; + break; + case MIPS_R5900: + switch (reg) + { + case REG_LO: + case REG_HI: + width = 128; + break; + case REG_LO1: + case REG_HI1: + width = 64; + break; + case R5900_SA: + case REG_VI: + case REG_VQ: + case REG_VR: // Technically 23-bit + case REG_VP: + width = 32; + break; + default: + if (reg >= REG_VI0 && reg <= REG_VI15) + width = 16; + else if (reg >= REG_VCCR_STATUS && reg <= REG_VCCR_CMSAR1) + width = 32; + else if (REG_ZERO <= reg && reg <= REG_RA) + width = 128; // 64; // 128 + else if (FPREG_F0 <= reg && reg <= FPREG_F31) + width = 32; + else if (reg >= REG_VACC && reg <= REG_VF31) + width = 128; + else if (reg >= REG_VACC_X && reg <= REG_VF31_W) + width = 32; + else if (reg >= REG_VACC_XY && reg <= REG_VF31_ZW) + width = 64; + else if (reg >= REG_VACC_XYZ && reg <= REG_VF31_YZW) + width = 96; + else if (reg >= REG_VACC_XYZW && reg <= REG_VF31_XYZW) + width = 128; + } + default: + break; + } + width /= 8; + return width <= maxWidth ? width : maxWidth; +} +#ifdef __cplusplus +} +}//end namespace +#endif
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