diff options
| author | Galen Williamson <galen@vector35.com> | 2025-04-04 22:01:15 -0400 |
|---|---|---|
| committer | Galen Williamson <galen@vector35.com> | 2025-04-08 15:40:49 -0400 |
| commit | e301d99a8df8ed185ffe71dabe915ab55d6fb885 (patch) | |
| tree | 599a48c86f8425b02362e9910b70dd12b954b128 /arch/mips | |
| parent | b0b223e9f2379c5d6622dcc082692aa94235cd96 (diff) | |
[aarch64] lift all LD[1-4]R? and ST[1-4] opcodes, lift ST/LDCLR, ST/LDEOR, ST/LDSET, and their variants
Also fixes all outstanding issues in arm64test.py, including intrinsics, dc, at, and tlbi
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/il.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/mips/il.cpp b/arch/mips/il.cpp index 97761e82..331d3d13 100644 --- a/arch/mips/il.cpp +++ b/arch/mips/il.cpp @@ -1174,23 +1174,23 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu il.Or(8, il.ShiftLeft(8, il.Register(4, REG_HI), il.Const(1, 32)), il.ZeroExtend(8, il.Register(4, REG_LO))))); il.AddInstruction(il.SetRegisterSplit(4, REG_HI, REG_LO, il.Sub(8, il.Register(8, LLIL_TEMP(0)), - il.MultDoublePrecUnsigned(8, ReadILOperand(il, instr, 1, registerSize), ReadILOperand(il, instr, 2, registerSize))))); + il.MultDoublePrecUnsigned(4, ReadILOperand(il, instr, 1, registerSize), ReadILOperand(il, instr, 2, registerSize))))); SignExtendHiLo(il, registerSize); break; case MIPS_MULT: - il.AddInstruction(il.SetRegisterSplit(4, REG_HI, REG_LO, il.MultDoublePrecSigned(8, ReadILOperand(il, instr, 1, registerSize), ReadILOperand(il, instr, 2, registerSize)))); + il.AddInstruction(il.SetRegisterSplit(4, REG_HI, REG_LO, il.MultDoublePrecSigned(4, ReadILOperand(il, instr, 1, registerSize), ReadILOperand(il, instr, 2, registerSize)))); SignExtendHiLo(il, registerSize); break; case MIPS_MULTU: - il.AddInstruction(il.SetRegisterSplit(4, REG_HI, REG_LO, il.MultDoublePrecUnsigned(8, ReadILOperand(il, instr, 1, registerSize), ReadILOperand(il, instr, 2, registerSize)))); + il.AddInstruction(il.SetRegisterSplit(4, REG_HI, REG_LO, il.MultDoublePrecUnsigned(4, ReadILOperand(il, instr, 1, registerSize), ReadILOperand(il, instr, 2, registerSize)))); SignExtendHiLo(il, registerSize); break; case MIPS_DMULT: - il.AddInstruction(il.SetRegisterSplit(8, REG_HI, REG_LO, il.MultDoublePrecSigned(16, ReadILOperand(il, instr, 1, registerSize), ReadILOperand(il, instr, 2, registerSize)))); + il.AddInstruction(il.SetRegisterSplit(8, REG_HI, REG_LO, il.MultDoublePrecSigned(8, ReadILOperand(il, instr, 1, registerSize), ReadILOperand(il, instr, 2, registerSize)))); break; case MIPS_DMULTU: - il.AddInstruction(il.SetRegisterSplit(8, REG_HI, REG_LO, il.MultDoublePrecUnsigned(16, ReadILOperand(il, instr, 1, registerSize), ReadILOperand(il, instr, 2, registerSize)))); + il.AddInstruction(il.SetRegisterSplit(8, REG_HI, REG_LO, il.MultDoublePrecUnsigned(8, ReadILOperand(il, instr, 1, registerSize), ReadILOperand(il, instr, 2, registerSize)))); break; case MIPS_NEG: case MIPS_NEGU: |